Abstract: The present disclosure relates to methods and apparatus for display processing. In some aspects, the apparatus can measure at least one panel including one or more panel measurements. The apparatus can also determine at least one correction factor for each of the one or more panel measurements. Further, the apparatus can adjust the at least one correction factor based on each of the one or more panel measurements. In some aspects, the apparatus can compress the at least one correction factor based on each of the one or more panel measurements. Moreover, the apparatus can store the compressed at least one correction factor. In some aspects, the apparatus can decode correction data for at least one frame based on the adjusted at least one correction factor. The apparatus can also store or communicate the decoded correction data for the at least one frame.

Abstract: The present disclosure relates to methods and apparatus for display processing. In some aspects, the apparatus can measure at least one panel including one or more panel measurements. The apparatus can also determine at least one correction factor for each of the one or more panel measurements. Further, the apparatus can adjust the at least one correction factor based on each of the one or more panel measurements. In some aspects, the apparatus can compress the at least one correction factor based on each of the one or more panel measurements. Moreover, the apparatus can store the compressed at least one correction factor. In some aspects, the apparatus can decode correction data for at least one frame based on the adjusted at least one correction factor. The apparatus can also store or communicate the decoded correction data for the at least one frame.

Abstract: A device configured to change a subpixel format from a non-native display device format to a native display format, includes a buffer configured to store compressed pixels in a sub-pixel format that is ordered in the non-native display device format. The device includes a processor, coupled to the buffer, configured to receive, from the buffer, a stream of the compressed pixels, and generate an uncompressed stream of the pixels with a stream compression decoder. The processor is configured to generate an ordered uncompressed stream of pixels in the native display device format by reordering the uncompressed stream of pixels in the sub-pixel format that is ordered in the non-native display format based on a reorder factor that is an integer multiple of a fundamental coding unit used in the stream compression decoder. The processor is configured to output the ordered uncompressed stream of pixels in the native display device format.

Abstract: Presented herein are caching structures and apparatus for use in block based video. In one embodiment, there is described a system receiving lower resolution frames and generating higher resolution frames. The system comprises an upsampling circuit, a first circuit, and a second circuit. The upsampling circuit upsamples a particular lower resolution frame, thereby resulting in an upsampled frame. The first circuit maps frames that are proximate to the particular frame, to the particular frame. The second circuit simultaneously updates the upsampled frame with two or more blocks from at least one of the frames that are proximate to the particular frame.

Abstract: A system for processing video information, the system including a memory configured to store video information, a memory controller coupled to the memory and configured to receive memory requests for the video information, a first video signal processing client coupled to the memory controller. The first video signal processing client including a video signal processor, a buffer coupled to the video signal processor, and a memory request module coupled to the memory controller and to the buffer, the memory request module being configured to submit amortized memory requests to the memory controller.

Abstract: Presented herein are caching structures and apparatus for use in block based video. In one embodiment, there is described a system receiving lower resolution frames and generating higher resolution frames. The system comprises an upsampling circuit, a first circuit, and a second circuit. The upsampling circuit upsamples a particular lower resolution frame, thereby resulting in an upsampled frame. The first circuit maps frames that are proximate to the particular frame, to the particular frame. The second circuit simultaneously updates the upsampled frame with two or more blocks from at least one of the frames that are proximate to the particular frame.

Abstract: Presented herein are caching structures and apparatus for use in block based video. In one embodiment, there is described a system for providing receiving lower resolution frames and generating higher resolution frames. The system comprises an integrated circuit. The integrated circuit comprises a first circuit, a direct memory access, and a cache. The first circuit maps frames that are proximate to a particular frame to the particular frame. The direct memory access fetches blocks from said proximate frames. The cache stores at least some of the blocks from said proximate frames.

Abstract: A system for processing video information, the system including a memory configured to store video information, a memory controller coupled to the memory and configured to receive memory requests for the video information, a first video signal processing client coupled to the memory controller. The first video signal processing client including a video signal processor, a buffer coupled to the video signal processor, and a memory request module coupled to the memory controller and to the buffer, the memory request module being configured to submit amortized memory requests to the memory controller.