Abstract: The invention relates to a method of measuring the thickness of a semiconductor substrate. First, a semiconductor substrate having a thickness and a photocurrent generating structure is provided. Next, the semiconductor substrate is exposed to a light source and a current generated by the light source is measured across the photocurrent generating structure. Finally, the thickness of the semiconductor substrate is determined by the current measurement.

Abstract: A method for accessing a portion of an integrated circuit formed on top of a semiconductor substrate from the bottom of the semiconductor substrate. First, alignment marks are located which are approximately aligned to the integrated circuit. These alignment marks are then used in conjunction with a circuit diagram of the integrated circuit to determine the point on the bottom of the semiconductor substrate residing beneath the portion of the integrated circuit which the practitioner desires to access. Finally, an opening is etched into the bottom of the semiconductor substrate at this point.

Abstract: A method and an apparatus for endpoint determination when milling an integrated circuit disposed in a substrate. In one embodiment, the substrate is charged to a first polarity while the well regions and active diffusion regions of the integrated circuit are charged to another polarity thus resulting in an electrical bias at the P-N junctions in the substrate. By powering up the integrated circuit in this fashion during milling, endpoint detection can be accurately determined by using a voltage contrast mechanism such as the imaging detector of a focused ion beam (FIB) milling tool. A diffusion boundary can also be determined in accordance with the teachings of the invention by the use of the stage current monitor of the FIB milling tool.

Abstract: A fiducial for aligning an integrated circuit die. In one embodiment, the fiducial is configured to be exposed by laser chemical etching through a silicon substrate through the back side of a C4 packaged integrated circuit die. The presently described fiducial includes floating diffusion regions disposed in the substrate. An oxide layer free of metal contacts is disposed over the diffusion regions within the fiducial region of the integrated circuit. A metal pattern layer is disposed beneath the oxide layer to provide alignment information. The metal pattern layer is configured to be visible through the oxide layer after the silicon substrate has been removed from the fiducial region. A light block is disposed between the metal pattern layer and an underlying epoxy underfill layer to minimize the risk of an excessive amount of light from being exposed to the underlying epoxy layer, which minimizes the risk of the epoxy layer from damaging the integrated circuit from excessive light exposure.

Abstract: A method and an apparatus for cooling a semiconductor die. In one embodiment, a C4 packaged semiconductor die is thermally coupled to a cooling plate having an opening. The opening of the cooling plate is disposed over a back side surface of the semiconductor die such that direct unobstructed access to the exposed back side surface of the semiconductor die is provided. A conformable thermal conductor, such as indium, is disposed between the semiconductor die and the cooling plate to improve the thermal coupling between the semiconductor and cooling plate. In one embodiment, the semiconductor die is mounted on a circuit board and a cooling block is disposed on the opposite side of the circuit board.

Abstract: A method and an apparatus for synchronizing a mode locked laser with a device under test. The present invention provides a stroboscopic technique that synchronizes the free running laser pulses of a mode locked laser to a DUT enabling the optical testing of integrated circuits to be performed and waveform measurements to be acquired from a DUT at random operating frequencies. In one embodiment, a laser synchronizing apparatus is configured to be used to test a device under test . The laser synchronizing apparatus includes a mode locked laser generating repeating laser pulses having a first period. A test pattern operating in M clocks when executed on the device under test is constructed. M is an integer and each one of the M clocks has a second period. A time per test pattern is computed such that the time per test pattern provides a sufficient amount of time to execute the constructed test pattern operating in the M clocks.

Abstract: An integrated circuit device having alignment marks that are located on the integrated circuit device semiconductor substrate and aligned to the integrated circuit. The alignment marks are used in conjunction with a circuit diagram of the integrated circuit to determine the point on the bottom of the semiconductor substrate residing beneath the portion of the integrated circuit which the practitioner desires to access.