Patents by Inventor Paul Wong

Paul Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070045831
    Abstract: A method and an apparatus for separating elongated semiconductor strips from a wafer of semiconductor material are disclosed. Vacuum is applied to the face of each semiconductor strip forming an edge of the wafer or being adjacent to the edge. The wafer and the source of the vacuum are displaced to separate each elongated semiconductor strip from the wafer. Further, a method and an apparatus for assembling elongated semiconductor strips separated from a wafer of semiconductor material into an array of strips are disclosed. Still further, methods, apparatuses, and systems for assembling an array of elongated semiconductor strips on a substrate are also disclosed.
    Type: Application
    Filed: May 7, 2004
    Publication date: March 1, 2007
    Inventors: Paul Wong, Razmik Abnoos, Vernie Everett, Mark Kerr
  • Publication number: 20060086403
    Abstract: The present disclosure relates to a device for the sealing of inflatable objects, in particular tires, comprising a gas pressure source, a pressure hose for the connection of the gas pressure source to the inflatable object and a sealing agent contained in a removal unit. In accordance with the present disclosure, the pressure hose simultaneously forms the removal unit containing the sealing agent.
    Type: Application
    Filed: September 29, 2005
    Publication date: April 27, 2006
    Inventors: Arne Kant, Manfred Zeuner, Rainer Samson, Paul Wong
  • Patent number: 6745356
    Abstract: The present invention relates to an improved digital circuit design employing scannable state elements. In one embodiment, a digital circuit design includes a first functional latch coupled to a first logic block and a second functional latch coupled to a second logic block. The functional latches are in separate scan chains and receive their own respective scan in inputs. The functional latches are both coupled to a common holding latch that captures content from the functional latches. In another embodiment, the digital circuit design includes two logic blocks that are coupled to a scannable state element. The functional latch is disposed within two different scan chains and receives scan in inputs from both scan chains. The functional latch may test the first and second logic blocks to provide controllability and observability. By sharing a common scannable state element, the invention reduces overhead and space in the circuit design.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: June 1, 2004
    Assignee: Fujitsu Limited
    Inventor: Paul Wong
  • Patent number: 6658617
    Abstract: An apparatus for obtaining valid values during a built-in self-testing of logic (“LBIST”) is disclosed. The apparatus includes a first multiplexer, a second multiplexer and a 1-hot init circuit. The 1-hot init circuit includes a scan register, a first inverter, a third multiplexer, a second inverter, and a fourth multiplexer. The scan register includes a plurality of state elements. The first multiplexer is coupled to receive a random data signal and an output of the 1-hot init circuit. Within the 1-hot init circuit, a next to last and a last state element of the scan register is coupled to the inverters and the third and fourth multiplexers, respectively. The first inverter is also coupled to the third multiplexer and the second inverter is coupled to the fourth multiplexer. The output of the fourth multiplexer is coupled to the input of the second multiplexer. Also coupled to the input of the second multiplexer is an input for the random data signal.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: December 2, 2003
    Assignee: Fujitsu Limited
    Inventor: Paul Wong
  • Patent number: 6636997
    Abstract: The initialization process and structure of the system ensure that during loading of random data a 1-hot condition is maintained to the 1-hot multiplexer so as to prevent contention or a high current state. The present invention further improves observability of intermediate stages by preventing random data feeding of the state elements in scan chains that cannot tolerate random data. A scan chain having only scan registers that can receive random data is referred to as a LBIST Random Scan Chain (LRSC) and a scan chain having one or more scan registers that cannot tolerate and cannot receive random data is referred to as a “LBIST Non-random Scan Chain” (LNSC). A PRPG generates random data having a plurality of bit values to the LRSCs which is then passed to a multiple input shift register (MISR). The LNSCs do not receive random data from the PRPG but instead receive bit values from another scan chain.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: October 21, 2003
    Assignee: Fujitsu Limited
    Inventors: Paul Wong, Mark O. Porter, Dwight K. Elvey
  • Patent number: 6572435
    Abstract: A confetti launcher is provided and includes a housing for storing the confetti, a rotatable actuator coupled to the housing, and a spring biased movable member disposed within an interior of the housing for ejecting the confetti. The movable member is positionable between a first position where it is locked relative to the actuator and a second position where it is free to move and an energy stored in a biasing element is released and translated into a force applied to the stored confetti such that the confetti is ejected from an open end of the housing.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: June 3, 2003
    Assignee: Mingway Industrial, Limited
    Inventor: Paul Wong
  • Patent number: 5835502
    Abstract: A method and apparatus for handling variable data word widths and array depths in an array built-in self-test system for testing a plurality of memory arrays using a single controller. Each array includes a predetermined row and column address depth and data word width. Each array further includes a scan register. A universal test data word is generated and sent to the scan register of each array. The universal length test data word has a length dependent upon the maximum row address depth, maximum column address depth and/or the maximum data word width. A portion of the test data word which exceeds the column address depth, row address depth and/or the data word width of a particular array is shifted off the end of the scan register of the particular array.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: November 10, 1998
    Assignee: International Business Machines Corporation
    Inventors: Anthony Gus Aipperspach, Todd Alan Christensen, Leland Leslie Day, Paul Allen Ganfield, Murali Vaddigiri, Paul Wong
  • Patent number: D388798
    Type: Grant
    Filed: March 7, 1996
    Date of Patent: January 6, 1998
    Assignee: Good Hope Industries, Ltd.
    Inventor: Paul Wong Wai Kan