Patents by Inventor Pauline Calka

Pauline Calka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096711
    Abstract: A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Qi Xie, Chiyu Zhu, Kiran Shrestha, Pauline Calka, Oreste Madia, Jan Willem Maes, Michael Eugene Givens
  • Patent number: 11532757
    Abstract: A semiconductor device and method for manufacturing the semiconductor device are disclosed. Specifically, the semiconductor device may include a charge trapping layer with improved retention and speed for VNAND applications. The charge trapping layer may comprise an aluminum nitride (AlN) or aluminum oxynitride (AlON) layer.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: December 20, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Pauline Calka, Qi Xie, Dieter Pierreux, Bert Jongbloed
  • Publication number: 20200227325
    Abstract: A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Qi Xie, Chiyu Zhu, Kiran Shrestha, Pauline Calka, Oreste Madia, Jan Willem Maes, Michael Eugene Givens
  • Patent number: 10607895
    Abstract: A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: March 31, 2020
    Assignee: ASM IP Holdings B.V.
    Inventors: Qi Xie, Chiyu Zhu, Kiran Shrestha, Pauline Calka, Oreste Madia, Jan Willem Maes, Michael Eugene Givens
  • Patent number: 10410943
    Abstract: A system and a method for passivating a surface of a semiconductor. The method includes providing the surface of the semiconductor to a reaction chamber of a reactor, exposing the surface of the semiconductor to a gas-phase metal containing precursor in the reaction chamber and exposing the surface of the semiconductor to a gas-phase chalcogenide containing precursor. The methods also include passivating the surface of the semiconductor using the gas-phase metal containing precursor and the gas-phase chalcogenide containing precursor to form a passivated surface.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: September 10, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Xiaoqiang Jiang, Fu Tang, Qi Xie, Pauline Calka, Sung-Hoon Jung, Michael Eugene Givens
  • Publication number: 20190088555
    Abstract: A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.
    Type: Application
    Filed: September 18, 2017
    Publication date: March 21, 2019
    Inventors: Qi Xie, Chiyu Zhu, Kiran Shrestha, Pauline Calka, Oreste Madia, Jan Willem Maes, Michael Eugene Givens
  • Publication number: 20180122959
    Abstract: A semiconductor device and method for manufacturing the semiconductor device are disclosed. Specifically, the semiconductor device may include a charge trapping layer with improved retention and speed for VNAND applications. The charge trapping layer may comprise an aluminum nitride (AlN) or aluminum oxynitride (AlON) layer.
    Type: Application
    Filed: October 6, 2017
    Publication date: May 3, 2018
    Inventors: Pauline Calka, Qi Xie, Dieter Pierreux, Bert Jongbloed
  • Publication number: 20180108587
    Abstract: A system and a method for passivating a surface of a semiconductor. The method includes providing the surface of the semiconductor to a reaction chamber of a reactor, exposing the surface of the semiconductor to a gas-phase metal containing precursor in the reaction chamber and exposing the surface of the semiconductor to a gas-phase chalcogenide containing precursor. The methods also include passivating the surface of the semiconductor using the gas-phase metal containing precursor and the gas-phase chalcogenide containing precursor to form a passivated surface.
    Type: Application
    Filed: August 9, 2017
    Publication date: April 19, 2018
    Inventors: Xiaoqiang Jiang, Fu Tang, Qi Xie, Pauline Calka, Sung-Hoon Jung, Michael Eugene Givens
  • Patent number: 9911676
    Abstract: Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase chalcogen precursor to passivate the high-mobility semiconductor surface.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: March 6, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Fu Tang, Michael E. Givens, Qi Xie, Xiaoqiang Jiang, Petri Raisanen, Pauline Calka
  • Publication number: 20170117202
    Abstract: Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase chalcogen precursor to passivate the high-mobility semiconductor surface.
    Type: Application
    Filed: January 3, 2017
    Publication date: April 27, 2017
    Inventors: Fu Tang, Michael E. Givens, Qi Xie, Xiaoqiang Jiang, Petri Raisanen, Pauline Calka