Abstract: A signal generation circuit that uses a waveform generation mechanism to generate predetermined waveform(s) when triggered. A triggering mechanism is configured to repeatedly trigger the waveform generation mechanism at times that are dependent on data provided by a data source. The predetermined waveform may be a bandwidth-limited pulse, but might also be a rising edge or a falling edge of a pulse. Various consecutive waveforms may be summed together to thereby formulate a continuous signal. The waveform may have particular characteristics by design.

Abstract: A signal generation circuit that uses a waveform generation mechanism to generate predetermined waveform(s) when triggered. A triggering mechanism is configured to repeatedly trigger the waveform generation mechanism at times that are dependent on data provided by a data source. The predetermined waveform may be a bandwidth-limited pulse, but might also be a rising edge or a falling edge of a pulse. Various consecutive waveforms may be summed together to thereby formulate a continuous signal. The waveform may have particular characteristics by design.

Abstract: A protection circuit for protecting an electronic circuit against EMC disturbances and/or negative transient overvoltage pulses comprises a switch in series between a power supply and the electronic circuit to be protected; a comparator for comparing a first operating parameter with a second operating parameter and producing a comparison signal, the comparison signal being used as a control signal for controlling opening and closing of the switch; and a delay circuit adapted for delaying closing of the switch. A corresponding method is also provided.

Abstract: An output driver circuit has an input, an output node, and first and second transistors coupled in series between the output node and a first source of operating potential. Parasitic diodes of the first and second transistors are anti-serially coupled. The output driver circuit has first and second control circuits coupled to control the first and second transistors respectively. The first transistor is controlled as a controlled current source depending on a signal at the input during normal conditions when the current that flows through the output is in a first direction, and the second control circuit controls the second transistor to prevent unwanted DC current at the output from flowing through the output in a second direction. The first and second transistors are also controlled to limit unwanted transient currents during an EMC disturbance substantially symmetrically.

Abstract: A method or apparatus is provided for detecting an error condition associated with a load (RL) or a connection (P) to the load (RL). The load (RL) may comprise an energy storing element (Cext). During a first diagnosis phase, it is determined whether the load (RL) or the connection (P) to the load (RL) is in a normal operation condition or in an error condition. If the load (RL) or the connection (P) to the load (RL) is in an error condition, during a second diagnosis phase it is determined whether the error condition is an open load condition, short circuit condition to ground or a short circuit condition to a power supply. When the load is in a starting state before the first diagnosis phase, the method or apparatus may further comprise carrying out, after the second diagnosis phase, a resetting phase for resetting the load to the starting state.

Abstract: A measurement method or system for measuring a physical value comprises, during a same clock cycle, forming an input signal, a reference signal and an offset signal, the input signal including a parasitic value and a useful measurement value. A relationship between the input signal where the parasitic value has been cancelled out, and the reference signal is derived. From this relationship, a value relating to the physical value is determined. The input signal, reference signal and offset signal are respectively associated with an input element, a reference element and a parasitic element. All elements have a common driving signal, and the parasitic value is depending on the common driving signal.

Abstract: A monotonic digital-to-analog converter (DAC) for converting a digital input signal into an analog output signal comprises: an input node for receiving the digital input signal having at least M+L bits, an output node for delivering the analog output signal corresponding to the received digital input signal, a coarse conversion block comprising current sources and first switching means for converting M more significant bits of the digital input signal into a coarse block output current, a fine conversion block comprising a current divider and second switching means for converting L less significant bits of the digital input signal into a corresponding current value, the fine conversion block having means for receiving current from a first unselected current source of the coarse conversion block, and a first cascode means for active cascoding the coarse block output current, a second cascode means, for active cascoding the current from the first unselected current source.

Abstract: A two-dimensional matrix decoder of a digital-to-analog converter comprises an array of current cells, the cells having a current source means or a current divider means and a switching means, all cells being activatable in a pre-determined sequence. The matrix decoder comprises: a selection means outputting a first selection signal for selecting a cell, a cell state signaling means outputting a cell state signal determining whether a cell comes before or after the selected cell in the pre-determined sequence, and matrix logic associated with each cell for generating a control signal suitable for controlling the switching means of that cell for switching current from the current source means or current divider means of that cell to at least one of a first node or a second node, the control signal being generated depending on the first selection signal and the cell state signal.

Abstract: A two-dimensional matrix decoder of a digital-to-analog converter comprises an array of current cells, the cells having a current source means or a current divider means and a switching means, all cells being activatable in a pre-determined sequence. The matrix decoder comprises: a selection means outputting a first selection signal for selecting a cell, a cell state signaling means outputting a cell state signal determining whether a cell comes before or after the selected cell in the pre-determined sequence, and matrix logic associated with each cell for generating a control signal suitable for controlling the switching means of that cell for switching current from the current source means or current divider means of that cell to at least one of a first node or a second node, the control signal being generated depending on the first selection signal and the cell state signal.

Abstract: A monotonic digital-to-analog converter (DAC) for converting a digital input signal into an analog output signal comprises:

Abstract: A measurement method or system for measuring a physical value comprises, during a same clock cycle, forming an input signal, a reference signal and an offset signal, the input signal including a parasitic value and a useful measurement value. A relationship between the input signal where the parasitic value has been cancelled out, and the reference signal is derived. From this relationship, a value relating to the physical value is determined. The input signal, reference signal and offset signal are respectively associated with an input element, a reference element and a parasitic element. All elements have a common driving signal, and the parasitic value is depending on the common driving signal.

Abstract: A method or apparatus is provided for detecting an error condition associated with a load (RL) or a connection (P) to the load (RL). The load (RL) may comprise an energy storing element (Cext). During a first diagnosis phase, it is determined whether the load (RL) or the connection (P) to the load (RL) is in a normal operation condition or in an error condition. If the load (RL) or the connection (P) to the load (RL) is in an error condition, during a second diagnosis phase it is determined whether the error condition is an open load condition, short circuit condition to ground or a short circuit condition to a power supply. When the load is in a starting state before the first diagnosis phase, the method or apparatus may further comprise carrying out, after the second diagnosis phase, a resetting phase for resetting the load to the starting state.