Patents by Inventor Pavel Roy Paladhi
Pavel Roy Paladhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136270Abstract: An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.Type: ApplicationFiled: October 23, 2022Publication date: April 25, 2024Inventors: Francesco PREDA, Sungjun CHUN, Jose A. HEJASE, Junyan TANG, Pavel ROY PALADHI, Nam Huu PHAM, Wiren Dale BECKER, Daniel Mark DREPS
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Publication number: 20240008186Abstract: A gang drilling machine for drilling a circuit card includes a pair of n and p master drills that are configured to be aligned in registry with respective n and p test vias of the card; pluralities of n and p minion drills that are configured to be aligned in registry with pluralities of n and p live vias of the card; and a controller that is electrically connected to control the n and p master drills and minion drills, and to send and receive electrical signals to and from the card. The controller is configured to: send a query signal to the card; monitor a response signal from the card; determine drilling depth of at least one of the master drills, in response to comparing the response signal to the query signal; and adjust operation of the machine, in response to the determined drilling depth.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Yanyan Zhang, Mahesh Bohra, Wiren Dale Becker, Nam Huu Pham, Pavel Roy Paladhi, Daniel Mark Dreps, Lloyd Andre Walls
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Publication number: 20230420394Abstract: A multi-chip package structure is provided. The multi-chip package structure includes a first IC chip and a second IC chip, and a fluid conduit thermally coupled to the first IC chip and the second IC chip. The multi-chip package structure is configured to remove heat generated by at least one of the first IC chip and the second IC chip. The fluid conduit has a first end and a second end opposite to the first end. The multi-chip package structure also includes a first monopole feed connected between the first IC chip and the first end of the fluid conduit, and a second monopole feed connected between the second IC chip and the second end of the fluid conduit. The first monopole feed is configured to transmit an electromagnetic signal through the fluid conduit toward the second monopole feed and vice versa.Type: ApplicationFiled: June 22, 2022Publication date: December 28, 2023Inventors: Anil Yuksel, Jose A. Hejase, Junyan Tang, Pavel Roy Paladhi, Joshua Myers
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Patent number: 11658378Abstract: Methods and apparatuses for vertically transitioning signals between substrate integrated waveguides within a multilayered printed circuit board (PCB) are disclosed. A first substrate integrated waveguide (SIW) is provided in a first layer of the PCB, the first SIW having a first terminal portion. A second SIW is provided in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion, wherein a first ground plane separates the first SIW and the second SIW. A vertical transition comprising an aperture in the first ground plane that is disposed in an area defined by the overlap of the first terminal portion and the second terminal portion, such that a signal propagated in the first SIW transitions to the second SIW in a different layer through the aperture.Type: GrantFiled: October 14, 2019Date of Patent: May 23, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joshua C. Myers, Jose A. Hejase, Junyan Tang, Pavel Roy Paladhi, Wiren D. Becker, Sungjun Chun, Daniel M. Dreps
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Patent number: 11399428Abstract: A printed circuit board (‘PCB’) including a substrate integrated waveguide (‘SIW’) formed using two ground planes representing the top and bottom walls of the waveguide, tightly pitched ground vias to act as two side walls and two back walls, and a pair of monopole antennas placed at each end of the SIW acting as signal feeding/receiving structures is disclosed. The waveguide dominant mode cut off frequency is determined by the spacing between the two side walls. Within each monopole antenna pair, the first monopole antenna operates at a first frequency while the second monopole antenna operates at another frequency. For each monopole antenna pair, the first monopole antenna and the second monopole antenna are located in the SIW at a distance from the back wall optimal for each operating frequency.Type: GrantFiled: October 14, 2019Date of Patent: July 26, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pavel Roy Paladhi, Jose A. Hejase, Junyan Tang, Joshua C. Myers, Sungjun Chun, Wiren D. Becker, Daniel M. Dreps
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Patent number: 11177665Abstract: A computer controls voltage supply for a system that includes a plurality of active cables. The computer determines that a first voltage source included in a first cable has failed to provide a required amount of voltage to the first cable. The computer switches the first cable to a second voltage source included in a second cable. The second voltage source provides voltage to the first cable.Type: GrantFiled: November 26, 2019Date of Patent: November 16, 2021Assignee: International Business Machines CorporationInventors: Pavel Roy Paladhi, Prasanna Jayaraman, Nam Huu Pham, Daniel M. Dreps
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Patent number: 11157274Abstract: A computer uses an active cable architecture to control communications. The computer sends a first set of instructions for completion of an activity to a first micro-controller of an active communication cable. The computer determines that at least one transceiver of an active cable is to receive a set of signals from the first micro-controller. The computer forms a communication connection between the first micro-controller and the at least one transceiver. The computer sends a second set of instructions to the at least one transceiver, wherein the second set of instructions instruct the at least one transceiver to complete at least a portion of the activity.Type: GrantFiled: November 26, 2019Date of Patent: October 26, 2021Assignee: International Business Machines CorporationInventors: Pavel Roy Paladhi, Prasanna Jayaraman, Nam Huu Pham, Daniel M. Dreps
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Publication number: 20210157579Abstract: A computer uses an active cable architecture to control communications. The computer sends a first set of instructions for completion of an activity to a first micro-controller of an active communication cable. The computer determines that at least one transceiver of an active cable is to receive a set of signals from the first micro-controller. The computer forms a communication connection between the first micro-controller and the at least one transceiver. The computer sends a second set of instructions to the at least one transceiver, wherein the second set of instructions instruct the at least one transceiver to complete at least a portion of the activity.Type: ApplicationFiled: November 26, 2019Publication date: May 27, 2021Inventors: Pavel Roy Paladhi, Prasanna Jayaraman, Nam Huu Pham, Daniel M. Dreps
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Publication number: 20210159707Abstract: A computer controls voltage supply for a system that includes a plurality of active cables. The computer determines that a first voltage source included in a first cable has failed to provide a required amount of voltage to the first cable. The computer switches the first cable to a second voltage source included in a second cable. The second voltage source provides voltage to the first cable.Type: ApplicationFiled: November 26, 2019Publication date: May 27, 2021Inventors: Pavel Roy Paladhi, Prasanna Jayaraman, Nam Huu Pham, Daniel M. Dreps
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Publication number: 20210111472Abstract: Methods and apparatuses for vertically transitioning signals between substrate integrated waveguides within a multilayered printed circuit board (PCB) are disclosed. A first substrate integrated waveguide (SIW) is provided in a first layer of the PCB, the first SIW having a first terminal portion. A second SIW is provided in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion, wherein a first ground plane separates the first SIW and the second SIW. A vertical transition comprising an aperture in the first ground plane that is disposed in an area defined by the overlap of the first terminal portion and the second terminal portion, such that a signal propagated in the first SIW transitions to the second SIW in a different layer through the aperture.Type: ApplicationFiled: October 14, 2019Publication date: April 15, 2021Inventors: JOSHUA C. MYERS, JOSE A. HEJASE, JUNYAN TANG, PAVEL ROY PALADHI, WIREN D. BECKER, SUNGJUN CHUN, DANIEL M. DREPS
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Publication number: 20210112655Abstract: A printed circuit board (‘PCB’) including a substrate integrated waveguide (‘SIW’) formed using two ground planes representing the top and bottom walls of the waveguide, tightly pitched ground vias to act as two side walls and two back walls, and a pair of monopole antennas placed at each end of the SIW acting as signal feeding/receiving structures is disclosed. The waveguide dominant mode cut off frequency is determined by the spacing between the two side walls. Within each monopole antenna pair, the first monopole antenna operates at a first frequency while the second monopole antenna operates at another frequency. For each monopole antenna pair, the first monopole antenna and the second monopole antenna are located in the SIW at a distance from the back wall optimal for each operating frequency.Type: ApplicationFiled: October 14, 2019Publication date: April 15, 2021Inventors: Pavel ROY PALADHI, Jose A. Hejase, Junyan Tang, Joshua C. Myers, Sungjun Chun, Wiren D. Becker, Daniel M. Dreps
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Patent number: 10705134Abstract: An apparatus, multi-layer semiconductor substrate and system for testing a high-speed signal through a printed circuit board is provided. Embodiment of the present invention provides an apparatus comprises a multi-layer substrate, one or more transmission lines disposed within the multi-layer substrate, one or more connectors attached to the multi-layer substrate for connecting one or more test cards, a lid, comprising one or more cutouts for the one or more connectors, a clamp for compressing the multi-layer substrate against the lid, and one or more high-speed connectors attached to the one or more test cards, respectively.Type: GrantFiled: December 4, 2017Date of Patent: July 7, 2020Assignee: International Business Machines CorporationInventors: Lloyd A. Walls, Nam H. Pham, Jason R. Eagle, Nathan L. Dunfee, Pavel Roy Paladhi
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Publication number: 20190170809Abstract: An apparatus, multi-layer semiconductor substrate and system for testing a high-speed signal through a printed circuit board is provided. Embodiment of the present invention provides an apparatus comprises a multi-layer substrate, one or more transmission lines disposed within the multi-layer substrate, one or more connectors attached to the multi-layer substrate for connecting one or more test cards, a lid, comprising one or more cutouts for the one or more connectors, a clamp for compressing the multi-layer substrate against the lid, and one or more high-speed connectors attached to the one or more test cards, respectively.Type: ApplicationFiled: December 4, 2017Publication date: June 6, 2019Inventors: Lloyd A. Walls, Nam H. Pham, Jason R. Eagle, Nathan L. Dunfee, Pavel Roy Paladhi
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Publication number: 20180113974Abstract: Mechanisms are provided for implementing a skew rate artificial neural network (ANN). The mechanisms generate a training dataset for training the skew rate ANN. The training dataset comprises a plurality of sets of data and each set of data corresponds to a particular set of printed circuit board (PCB) and communication channel characteristics. The mechanisms train the skew rate ANN based on the training dataset to generate a trained skew rate ANN. The mechanisms then receive an input dataset representing a set of PCB and communication channel characteristics for a PCB design. The trained skew rate ANN generates a predicted skew factor for the PCB design based on the input dataset. The predicted skew factor is then output to a PCB design tool to modify the PCB design based on the predicted skew factor.Type: ApplicationFiled: October 21, 2016Publication date: April 26, 2018Inventors: Dylan J. Boday, Zhaoqing Chen, Jose A. Hejase, Roger S. Krabbenhoft, Pavel Roy Paladhi, Junyan Tang