Patents by Inventor Pavithra Devaraj

Pavithra Devaraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11487548
    Abstract: A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 1, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Vijay Chinchole, Nisha Padattil Kuliyampattil, Sonam Agarwal, Akash Agarwal, Pavithra Devaraj, Yan Li
  • Patent number: 11080059
    Abstract: A method for reducing firmware size and increasing firmware performance. Core timing control conditions used by a die controller are converted into production ready core timing control conditions, from which firmware instructions are then generated. The production ready core timing control conditions comprise a plurality of fixed core timing control conditions. The firmware instructions are modified to determine core timing control condition values for fixed core timing control conditions before implementing storage operations, to store the core timing control condition values in global condition registers, and to modify references to fixed core timing control conditions to access the values in those global condition registers. Finally, the modified firmware instructions are stored on the die controller, which comprises a microcontroller configured to execute them.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: August 3, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Sonam Agarwal, Vijay Sukhlal Chinchole, Pavithra Devaraj
  • Publication number: 20210157607
    Abstract: A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Vijay Chinchole, Nisha Padattil Kuliyampattil, Sonam Agarwal, Akash Agarwal, Pavithra Devaraj, Yan Li