Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Abstract: An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.

Abstract: In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.

Abstract: An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.

Abstract: In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed.