Patents by Inventor Pavol Dudesek

Pavol Dudesek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10892097
    Abstract: A dielectric ceramic composition, a method for producing a dieelctric composition and the use of the dielectric composition are disclosed. In an embodiment a ceramic composition includes a main component with a quantity ratio Mg(1+x)(1?y)O3+xA(1+x)ySi(1?z)Dz and a remainder comprising contaminants, wherein 0.01×0.30, wherein 0.00?y?0.20, and wherein 0.00?z?1.00.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: January 12, 2021
    Assignee: TDK ELECTRONICS AG
    Inventor: Pavol Dudesek
  • Publication number: 20200385304
    Abstract: Doped, low-temperature co-fired ceramic (LTCC) insulating substrates and related wiring boards and methods of manufacture are disclosed. The doped, LTCC insulating substrate is formed from a baked (e.g., sintered) glass-ceramic aggregate material formed from a glass material, a ceramic filler material, and a composite oxide. The crystallized glass-ceramic aggregate is then doped with Iron and/or Manganese before baking. Iron or Manganese can further reduce dielectric loss and the loss tangent of the LTCC insulating substrate formed from that glass material. The glass material becomes crystallized due to an oxide crystal phase being deposited on the glass material during baking, which reduces the dielectric losses. This may be important for the application use as wiring boards for high radio-frequency (RF) electrical circuits where low dielectric loss and loss tangent is desired to achieve a desired signal transmission delay performance.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Inventors: Klaus Dieter Aichholzer, Pavol Dudesek, Pascal Dotta
  • Patent number: 10858282
    Abstract: Doped, low-temperature co-fired ceramic (LTCC) insulating substrates and related wiring boards and methods of manufacture are disclosed. The doped, LTCC insulating substrate is formed from a baked (e.g., sintered) glass-ceramic aggregate material formed from a glass material, a ceramic filler material, and a composite oxide. The crystallized glass-ceramic aggregate is then doped with Iron and/or Manganese before baking. Iron or Manganese can further reduce dielectric loss and the loss tangent of the LTCC insulating substrate formed from that glass material. The glass material becomes crystallized due to an oxide crystal phase being deposited on the glass material during baking, which reduces the dielectric losses. This may be important for the application use as wiring boards for high radio-frequency (RF) electrical circuits where low dielectric loss and loss tangent is desired to achieve a desired signal transmission delay performance.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 8, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Klaus Dieter Aichholzer, Pavol Dudesek, Pascal Dotta
  • Patent number: 10389105
    Abstract: An overvoltage protection element and a method for producing an overvoltage protection element is disclosed. In an embodiment, the overvoltage protection element includes a first electrode, a second electrode and a discharge region arranged between the first electrode and the second electrode, wherein a porous discharge dielectric is arranged in the discharge region, and wherein the overvoltage protection element is configured to discharge a gas in pores of the discharge dielectric and produce an electrically conductive connection between the first electrode and the second electrode.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: August 20, 2019
    Assignee: EPCOS AG
    Inventors: Manfred Schweinzger, Stefan Obermair, Pavol Dudesek
  • Publication number: 20190013149
    Abstract: A dielectric ceramic composition, a method for producing a dieelctric composition and the use of the dielectric composition are disclosed. In an embodiment a ceramic composition includes a main component with a quantity ratio Mg(1+x)(1?y)O3+xA(1+x)ySi(1?z)Dz and a remainder comprising contaminants, wherein 0.01×0.30, wherein 0.00?y?0.20, and wherein 0.00?z?1.00.
    Type: Application
    Filed: January 16, 2017
    Publication date: January 10, 2019
    Inventor: Pavol Dudesek
  • Patent number: 9865381
    Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: January 9, 2018
    Assignee: EPCOS AG
    Inventors: Yasuharu Miyauchi, Pavol Dudesek, Christian Faistauer, Gerhard Fuchs, Stefan Obermair, Klaus-Dieter Aichholzer, Christian Block, Sebastian Brunner
  • Publication number: 20170332491
    Abstract: For a carrier plate, it is proposed to brace a first ceramic functional layer over a connecting layer (VS) with a ceramic stressing layer (SPS) in order to reduce the lateral sintering shrinkage. The functional layer (FS) and the stressing layer (SPS) are glass-free or have only a small glass content of less than 5 wt %, whereas the connecting layer (VS) comprises a glass component or is a glass layer.
    Type: Application
    Filed: December 15, 2015
    Publication date: November 16, 2017
    Inventors: Yasuharu MIYAUCHI, Pavol DUDESEK, Edmund PAYR, Günther PUDMICH
  • Publication number: 20170236634
    Abstract: A film stack made from compacted green films and capable of being sintered to form a ceramic component with monolithic multi-layer structure is disclosed. The film stack includes a functional layer comprising a green film comprising a functional ceramic and a tension layer comprising a green film comprising a dielectric material. The tension layer is directly adjacent to the functional layer in the multi-layer structure. The multilayer structure also includes a first metallization plane and second metallization plane. The functional layer is between the first metallization plane and the second metallization plane.
    Type: Application
    Filed: November 22, 2016
    Publication date: August 17, 2017
    Inventors: Christian Block, Pavol Dudesek, Thomas Feichtinger, Christian Hoffmann, Guenter Pudmich
  • Publication number: 20170011827
    Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.
    Type: Application
    Filed: January 2, 2015
    Publication date: January 12, 2017
    Inventors: Yasuharu Miyauchi, Pavol Dudesek, Christian Faistauer, Gerhard Fuchs, Stefan Obermair, Klaus-Dieter Aichholzer, Christian Block, Sebastian Brunner
  • Patent number: 9532454
    Abstract: A film stack made from compacted green films and capable of being sintered to form a ceramic component with monolithic multi-layer structure is disclosed. The film stack includes a functional layer comprising a green film comprising a functional ceramic and a tension layer comprising a green film comprising a dielectric material. The tension layer is directly adjacent to the functional layer in the multi-layer structure. The multilayer structure also includes a first metallization plane and a second metallization plane. The functional layer is between the first metallization plane and the second metallization plane.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: December 27, 2016
    Assignee: EPCOS AG
    Inventors: Christian Block, Pavol Dudesek, Thomas Feichtinger, Christian Hoffmann, Guenter Pudmich
  • Publication number: 20160329698
    Abstract: An overvoltage protection element and a method for producing an overvoltage protection element is disclosed. In an embodiment, the overvoltage protection element includes a first electrode, a second electrode and a discharge region arranged between the first electrode and the second electrode, wherein a porous discharge dielectric is arranged in the discharge region, and wherein the overvoltage protection element is configured to discharge a gas in pores of the discharge dielectric and produce an electrically conductive connection between the first electrode and the second electrode.
    Type: Application
    Filed: January 15, 2015
    Publication date: November 10, 2016
    Inventors: Manfred Schweinzger, Stefan Obermair, Pavol Dudesek
  • Patent number: 8970324
    Abstract: A multilayer component includes a dielectric ceramic material that can be co-sintered with a varistor ceramic to form a monolithic multilayer component according to the invention. The multilayer component therefore includes a layer of a varistor ceramic and another layer of a dielectric. Both layers can be arranged directly adjacent to one another in the multilayer component. In the multilayer component, metallizations are arranged on or between the ceramic layers. The metallizations are structured to form conductor sections and metallized areas. The metallizations form together with the ceramic layers alongside a varistor at least one further component selected from at least one of the component functions.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: March 3, 2015
    Assignee: Epcos AG
    Inventors: Pavol Dudesek, Guenter Pudmich, Hannes Schiechl, Edmund Payr, Thomas Feichtinger, Werner Salz, Christian Hoffmann
  • Patent number: 8730648
    Abstract: An electrical component includes a ceramic base body. The ceramic base body includes several ceramic layers including a function layer and a composite layer bordering the function layer. The composite layer can include a zirconium oxide-glass filler mixture.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: May 20, 2014
    Assignee: Epcos AG
    Inventors: Uwe Wozniak, Thomas Feichtinger, Hermann Gruenbichler, Pavol Dudesek, Thomas Puerstinger
  • Publication number: 20120032757
    Abstract: A multilayer component includes a dielectric ceramic material that can be co-sintered with a varistor ceramic to form a monolithic multilayer component according to the invention. The multilayer component therefore includes a layer of a varistor ceramic and another layer of a dielectric. Both layers can be arranged directly adjacent to one another in the multilayer component. In the multilayer component, metallizations are arranged on or between the ceramic layers. The metallizations are structured to form conductor sections and metallized areas. The metallizations form together with the ceramic layers alongside a varistor at least one further component selected from at least one of the component functions.
    Type: Application
    Filed: February 8, 2010
    Publication date: February 9, 2012
    Applicant: EPCOS AG
    Inventors: Pavol Dudesek, Guenter Pudmich, Hannes Schiechl, Edmund Payr, Thomas Feichtinger, Werner Salz, Christian Hoffmann
  • Patent number: 7816293
    Abstract: A ceramic mixed system is proposed that includes a two-phase mixture of pure components A and B, wherein phase A is based on the cubic to tetragonal modification of Bi3NbO7 and phase B is based on a monoclinic pyrochlore modification of Bi2(Zn2/3Nb4/3)O7. The electrical properties of ceramics produced therefrom make the material suitable for components having a multilayer structure in which capacitors and inductors are integrated and which can be used in data processing or signal processing.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: October 19, 2010
    Assignee: EPCOS AG
    Inventors: Pavol Dudesek, Christian Hoffman, Matjaz Valant, Danilo Suvorov
  • Publication number: 20100014213
    Abstract: An electrical component includes a ceramic base body. The ceramic base body includes several ceramic layers including a function layer and a composite layer bordering the function layer. The composite layer can include a zirconium oxide-glass filler mixture.
    Type: Application
    Filed: October 20, 2006
    Publication date: January 21, 2010
    Inventors: Uwe Wozniak, Thomas Feichtinger, Hermann Gruenbichler, Pavol Dudesek, Thomas Puerstinger
  • Publication number: 20090155624
    Abstract: A ceramic mixed system is proposed that includes a two-phase mixture of pure components A and B, wherein phase A is based on the cubic to tetragonal modification of Bi3NbO7 and phase B is based on a monoclinic pyrochlore modification of Bi2(Zn2/3Nb4/3)O7. The electrical properties of ceramics produced therefrom make the material suitable for components having a multilayer structure in which capacitors and inductors are integrated and which can be used in data processing or signal processing.
    Type: Application
    Filed: November 21, 2008
    Publication date: June 18, 2009
    Inventors: Pavol Dudesek, Christian Hoffmann, Matjaz Valant, Danilo Suvorov
  • Publication number: 20090035560
    Abstract: A film stack made from compacted green films and capable of being sintered to form a ceramic component with monolithic multi-layer structure is disclosed. The film stack includes a functional layer comprising a green film comprising a functional ceramic and a tension layer comprising a green film comprising a dielectric material. The tension layer is directly adjacent to the functional layer in the multi-layer structure. The multilayer structure, also includes a first metallization plane and a second metallization plane. The functional layer is between the first metallization plane and the second metallization plane.
    Type: Application
    Filed: January 3, 2007
    Publication date: February 5, 2009
    Inventors: Christian Block, Pavol Dudesek, Thomas Feichtinger, Christian Hoffmann, Guenter Pudmich