Patents by Inventor Pawan Gogna

Pawan Gogna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9509400
    Abstract: An implantable bio-sensing platform architecture that enables the wireless selection, calibration and reading of multiple sensors, as well as checking the power levels of the solar powering source energizing various electronic and optoelectronic devices and circuits embedded in the platform. It also permits checking the operation of the potentiostats interfacing with each amperometric analyte sensor. The platform is flexible to include FET based sensors for protein sensing as well as other applications including pH sensing. In addition, other physiological sensors can be integrated in the platform.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: November 29, 2016
    Inventors: Faquir C Jain, Fotios Papadimitrakopoulos, Robert A Croce, Jr., Pawan Gogna, Syed Kamrul Islam, Liang Zuo, Kai Zhu
  • Publication number: 20160254863
    Abstract: An implantable bio-sensing platform architecture that enables the wireless selection, calibration and reading of multiple sensors, as well as checking the power levels of the solar powering source energizing various electronic and optoelectronic devices and circuits embedded in the platform. It also permits checking the operation of the potentiostats interfacing with each amperometric analyte sensor. The platform is flexible to include FET based sensors for protein sensing as well as other applications including pH sensing. In addition, other physiological sensors can be integrated in the platform.
    Type: Application
    Filed: May 9, 2016
    Publication date: September 1, 2016
    Inventors: Faquir C. Jain, Fotios Papadimitrakopoulos, Robert A. Croce, JR., Pawan Gogna, Syed Kamrul Islam, Liang Zuo, Kai Zhu
  • Patent number: 6191830
    Abstract: An electro-optic display device having a matrix array of picture elements and a thin film structure of storage capacitors associated with each picture element, the device provided with redundancy in the storage capacitor structure by segmenting one of the capacitor plates into two plates to produce two capacitors in series. Because the segmented plates are all on one level of the thin film structure, no additional masking steps are required.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: February 20, 2001
    Assignee: Philips Electronics North America Corporation
    Inventors: Pawan Gogna, Peter J. Janssen
  • Patent number: 6023309
    Abstract: A reflective liquid crystal display such as an AMLCD includes an array of reflective pixels located over a surface of a silicon substrate, with light transmissive regions being located between the reflective pixels. The structure includes two metal layers between the reflective pixels and the silicon substrate surface, with segments of one metal layer extending in a first direction to form row electrodes of the LCD and segments of the other metal layer extending in a second direction substantially perpendicular to the first to form column electrodes of the LCD. In order to block light that would otherwise pass through light transmissive regions between the reflective pixels, portions of the first two metal layers extend beneath the light transmissive regions between the reflective pixels. In this manner, a light-blocking function is provided without the need for a separate blocking or shading metal layer.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: February 8, 2000
    Assignee: Philips Electronics North America Corporation
    Inventors: Pawan Gogna, Peter J. Janssen
  • Patent number: 5977832
    Abstract: A method of biasing an MOS IC includes the steps of providing the IC with two MOS transistors having substantially similar characteristics and maintaining these two transistors at different temperatures. During operation of the IC, an output voltage is generated from each of the two transistors, and a bias voltage is generated as a function of the difference between the two output voltages. This bias voltage is then fed back to the gate terminals of the two MOS transistors to set the bias voltage to a steady-state level at which the circuit will operate at a zero temperature coefficient point. This bias voltage is also coupled to the gate electrodes of other transistors within the IC, to operate these transistors at the zero temperature coefficient point. An IC operated in accordance with biasing method will exhibit superior stability with variations in ambient temperature.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: November 2, 1999
    Assignee: Philips Electronics North America Corporation
    Inventors: Srinagesh Satyanarayana, Pawan Gogna