Patents by Inventor Pawel Owczarczyk
Pawel Owczarczyk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240086608Abstract: Embodiments include exerciser device placement in the development of an integrated circuit. Aspects of the invention include obtaining a design of an integrated circuit and creating a dynamic power blockage map for the integrated circuit. Aspects also include updating the integrated circuit design by placing one or more exercisers on the integrated circuit, wherein a location of the one or more exercisers on the integrated circuit is based on at least in part on the dynamic power blockage map. Based on a determination that the updated integrated circuit design complies with one or more design constraints, aspects further include outputting the updated integrated circuit design.Type: ApplicationFiled: September 8, 2022Publication date: March 14, 2024Inventors: Michael Romain, Lucas Dane LaLima, Michael Greene, Alper Buyuktosunoglu, Christopher Joseph Berry, Pawel Owczarczyk, Mark Cichanowski, William V. Huott, OFER GEVA, Jesse Peter Surprise, Eduard Herkel
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Patent number: 11817697Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.Type: GrantFiled: April 5, 2022Date of Patent: November 14, 2023Assignee: International Business Machines CorporationInventors: Adam Benjamin Collura, Michael Romain, William V. Huott, Pawel Owczarczyk, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Alper Buyuktosunoglu, Tobias Webel, Michael Joseph Cadigan, Jr., Paul Jacob Logsdon, Sean Michael Carey, Stefan Payer, Karl Evan Smock Anderson, Mark Cichanowski
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Publication number: 20230318286Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.Type: ApplicationFiled: April 5, 2022Publication date: October 5, 2023Inventors: Adam Benjamin COLLURA, Michael ROMAIN, William V. HUOTT, Pawel OWCZARCZYK, Christian JACOBI, Anthony SAPORITO, Chung-Lung K. SHUM, Alper BUYUKTOSUNOGLU, Tobias WEBEL, Michael Joseph CADIGAN, JR., Paul Jacob LOGSDON, Sean Michael CAREY, Stefan PAYER, Karl Evan Smock ANDERSON, Mark CICHANOWSKI
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Patent number: 11322439Abstract: Aspects of the invention include forming a semiconductor device. Gates are formed in a first direction over fins, the gates including gate material, the fins being formed in a second direction. Fin interconnects are formed in the first direction over the fins. A dielectric material is formed on the fins, and capacitor interconnects are formed over portions of the dielectric material in the first direction over the fins.Type: GrantFiled: November 13, 2019Date of Patent: May 3, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Sperling, Erik English, Akil Khamisi Sutton, Pawel Owczarczyk
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Patent number: 11281249Abstract: Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.Type: GrantFiled: September 23, 2019Date of Patent: March 22, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erik English, Akil Khamisi Sutton, Pawel Owczarczyk, Michael Sperling
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Patent number: 11204635Abstract: Aspects of the invention include a circuit having a power supply sensitive delay circuit, a variable delay circuit coupled to the power supply sensitive delay circuit, a delay line coupled to the variable delay circuit, and a logic circuit coupled to the delay line.Type: GrantFiled: September 23, 2019Date of Patent: December 21, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Sperling, Pawel Owczarczyk, Akil Khamisi Sutton, Erik English
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Patent number: 11152920Abstract: Aspects of the invention relate to an apparatus having a transmission gate coupled to a delay element and including a first transistor and a second transistor. A first node is coupled to a first gate of the first transistor, a first current source, and a first resistive element, an opposite end of the first resistive element being coupled to a ground potential. A second node is coupled to a second gate of the second transistor, a second current source, and a second resistive element, an opposite end of the second resistive element being coupled to a power supply.Type: GrantFiled: September 23, 2019Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Sperling, Akil Khamisi Sutton, Pawel Owczarczyk, Erik English
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Publication number: 20210143095Abstract: Aspects of the invention include forming a semiconductor device. Gates are formed in a first direction over fins, the gates including gate material, the fins being formed in a second direction. Fin interconnects are formed in the first direction over the fins. A dielectric material is formed on the fins, and capacitor interconnects are formed over portions of the dielectric material in the first direction over the fins.Type: ApplicationFiled: November 13, 2019Publication date: May 13, 2021Inventors: Michael Sperling, Erik English, Akil Khamisi Sutton, Pawel Owczarczyk
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Publication number: 20210091753Abstract: Aspects of the invention relate to an apparatus having a transmission gate coupled to a delay element and including a first transistor and a second transistor. A first node is coupled to a first gate of the first transistor, a first current source, and a first resistive element, an opposite end of the first resistive element being coupled to a ground potential. A second node is coupled to a second gate of the second transistor, a second current source, and a second resistive element, an opposite end of the second resistive element being coupled to a power supply.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Michael Sperling, Akil Khamisi Sutton, Pawel Owczarczyk, Erik English
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Publication number: 20210089104Abstract: Aspects of the invention include a circuit having a power supply sensitive delay circuit, a variable delay circuit coupled to the power supply sensitive delay circuit, a delay line coupled to the variable delay circuit, and a logic circuit coupled to the delay line.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Michael Sperling, Pawel Owczarczyk, Akil Khamisi Sutton, Erik English
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Publication number: 20210089071Abstract: Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Erik English, Akil Khamisi Sutton, Pawel Owczarczyk, Michael Sperling
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Patent number: 10931269Abstract: Aspects of the invention include a process for receiving data and a first clock signal of a first chip and a second clock signal of a second chip, the data being received on a data path and the first clock signal being received on a clock signal path, and determining that the first clock signal is arriving before the second clock signal by a difference quantity. Also, the process includes adding delay to the data path and the clock signal path according to the difference quantity.Type: GrantFiled: October 3, 2019Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Sperling, Pawel Owczarczyk, Chad Andrew Marquart, Douglas Malone
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Patent number: 10833653Abstract: Aspects of the invention include a circuit including a power circuit having an amplifier, a resistor, a current source, and a first node, one end of the resistor being configured to couple to a power supply, the first node being coupled to an opposite end of the resistor, a first input terminal of the amplifier, and the current source. A voltage sensitive circuit includes a logic gate coupled to both a second input terminal of the amplifier and an output terminal of the amplifier at a second node.Type: GrantFiled: September 23, 2019Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Sperling, Akil Khamisi Sutton, Pawel Owczarczyk, Erik English
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Patent number: 10797712Abstract: A technique relates to a digital phase locked loop (DPLL) including a digitally controlled oscillator (DCO), the DCO having delay elements and a current fill factor corresponding to a proportion of the delay elements in operation. A voltage regulator controller is operable to obtain a result of a comparison between a predefined fill factor and the current fill factor, the voltage regulator controller being operable to adjust voltage supplied to the DCO based on the result, the predefined fill factor indicating a predetermined proportion of the delay elements to be in operation.Type: GrantFiled: September 6, 2019Date of Patent: October 6, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pawel Owczarczyk, Michael Sperling, Miguel E. Perez
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Patent number: 10425088Abstract: According to one or more embodiments, a method implemented by a digital phase-locked loop of a processor is provided. The method includes turning off, by the digital phase-locked loop, a percentage of active devices of a digitally controlled oscillator to implement a fast path within the digital phase-locked loop. The method also includes reducing, by the digital phase-locked loop, a multiplier of a frequency filter setting to implement a control path within the digital phase-locked loop.Type: GrantFiled: January 19, 2017Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul D. Muench, Pawel Owczarczyk
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Patent number: 10230360Abstract: The present invention provides a system and method of increasing the resolution of on-chip timing uncertainty measurements. In an embodiment, the system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circuits, a clock circuit logically coupled to each of the tiers of flip-flop circuits respectively, and where the plurality of flip-flop circuits is logically configured, in response to a delay input of a first delay circuit in the set of delay circuits receiving an output from a programmable delay circuit and in response to receiving skewed clock signals from the clock circuits, to indicate how far within the plurality of flip-flop circuits an edge signal transmitted from the delay output of the each of the delay circuits propagated, respectively.Type: GrantFiled: June 16, 2017Date of Patent: March 12, 2019Assignee: International Business Machines CorporationInventors: Christos Vezyrtzis, Pawel Owczarczyk
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Publication number: 20180367128Abstract: The present invention provides a system and method of increasing the resolution of on-chip timing uncertainty measurements. In an embodiment, the system includes a set of delay circuits logically coupled in a chain configuration, a plurality of flip-flop circuits logically coupled to the delay output of the each of the delay circuits respectively, forming tiers of flip-flop circuits, a clock circuit logically coupled to each of the tiers of flip-flop circuits respectively, and where the plurality of flip-flop circuits is logically configured, in response to a delay input of a first delay circuit in the set of delay circuits receiving an output from a programmable delay circuit and in response to receiving skewed clock signals from the clock circuits, to indicate how far within the plurality of flip-flop circuits an edge signal transmitted from the delay output of the each of the delay circuits propagated, respectively.Type: ApplicationFiled: June 16, 2017Publication date: December 20, 2018Inventors: Christos Vezyrtzis, Pawel Owczarczyk
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Patent number: 10156882Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.Type: GrantFiled: October 9, 2015Date of Patent: December 18, 2018Assignee: International Business Machines CorporationInventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
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Patent number: 10152107Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.Type: GrantFiled: October 27, 2015Date of Patent: December 11, 2018Assignee: International Business Machines CorporationInventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
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Publication number: 20180205385Abstract: According to one or more embodiments, a method implemented by a digital phase-locked loop of a processor is provided. The method includes turning off, by the digital phase-locked loop, a percentage of active devices of a digitally controlled oscillator to implement a fast path within the digital phase-locked loop. The method also includes reducing, by the digital phase-locked loop, a multiplier of a frequency filter setting to implement a control path within the digital phase-locked loop.Type: ApplicationFiled: January 19, 2017Publication date: July 19, 2018Inventors: Paul D. Muench, Pawel Owczarczyk