Abstract: A method and system for enabling auto shut-off of programming of a non-volatile memory cell is disclosed. The system includes a memory array having a plurality of memory cells, each cell storing one bit of data. During the programming process, programming signals are applied to the target memory cells. A predefined period of time after the programming signals are applied, the auto shut-off system begins sensing an output signal from the memory cell. After the system detects an output signal from the memory cell, the system waits for a second predefined period of time before turning off the programming voltages. The system may be configured to sense an output voltage from the memory cell. The system then compares the output voltage to a reference voltage in order to detect when the cell is programmed. Alternatively, the system may sense an output current from the memory cell. The system then compares the output current to a reference current to detect when the cell is programmed.

Abstract: A method and system for enabling auto shut-off of programming of a non-volatile memory cell is disclosed. The system includes a memory array having a plurality of memory cells, each cell storing one bit of data. During the programming process, programming signals are applied to the target memory cells. A predefined period of time after the programming signals are applied, the auto shut-off system begins sensing an output signal from the memory cell. After the system detects an output signal from the memory cell, the system waits for a second predefined period of time before turning off the programming voltages. The system may be configured to sense an output voltage from the memory cell. The system then compares the output voltage to a reference voltage in order to detect when the cell is programmed. Alternatively, the system may sense an output current from the memory cell. The system then compares the output current to a reference current to detect when the cell is programmed.

Abstract: To provide a boundaryless burst mode access, a memory array is divided into two or more subarrays. Each subarray has its own row and column decoders. The columns of each subarray are divided into groups. A sense amplifier circuit is provided for each group of columns. The column decoder of each subarray selects simultaneously one column from each group so that the memory locations in one row in the selected columns have consecutive addresses. The memory locations in the selected row and columns are read by the sense amplifier circuits. While the contents of the sense amplifier circuits of one subarray are transferred one by one to the memory output, consecutive memory locations of another subarray are read to the sense amplifier circuits. In some embodiments, to save power, sense amplifier circuits are disabled when their outputs are not transferred to the memory output.