Patents by Inventor Pedram Sotoodeh Shahnani

Pedram Sotoodeh Shahnani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11115244
    Abstract: A signal isolator integrated circuit package includes a first circuit having a first input and a first output, a second circuit having a second input and a second output, an isolation barrier layer between the first circuit and the second circuit, wherein the second output of the second circuit is coupled to the first input of the first circuit through the isolation barrier. The signal isolator includes a comparator configured to compare the first input of the first circuit to the second output of the second circuit. The second output can be configured to convey at least three states, including a first state indicative of a logical high of an input signal received at the first input, a second state indicative of a logical low of the input signal, and a third state indicative of a fault condition.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 7, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Pedram Sotoodeh Shahnani, Cory Voisine
  • Publication number: 20210083907
    Abstract: A signal isolator integrated circuit package includes a first circuit having a first input and a first output, a second circuit having a second input and a second output, an isolation barrier layer between the first circuit and the second circuit, wherein the second output of the second circuit is coupled to the first input of the first circuit through the isolation barrier. The signal isolator includes a comparator configured to compare the first input of the first circuit to the second output of the second circuit. The second output can be configured to convey at least three states, including a first state indicative of a logical high of an input signal received at the first input, a second state indicative of a logical low of the input signal, and a third state indicative of a fault condition.
    Type: Application
    Filed: March 5, 2020
    Publication date: March 18, 2021
    Applicant: Allegro MicroSystems, LLC
    Inventors: Robert A. Briano, Pedram Sotoodeh Shahnani, Cory Voisine