Patents by Inventor PEDRO B. ZANETTA

PEDRO B. ZANETTA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190052228
    Abstract: A source follower method, system, and apparatus provide rail-to-rail capability to an output voltage terminal of a voltage follower feedback biased CMOS output circuit by providing a control circuit which includes first and second bypass transistors that are connected in parallel between first and second control circuit input/output terminals and controlled, respectively, by first and second control circuit inputs, and which also includes first and second current sources for injecting source and sink currents in the output node as a function, respectively, of a first bypass current through the first bypass transistor which turns ON when the output voltage rises above a top threshold voltage level and of a second bypass current through the second bypass transistor which turns ON when the output voltage falls below a bottom threshold voltage level.
    Type: Application
    Filed: August 11, 2017
    Publication date: February 14, 2019
    Applicant: NXP USA, Inc.
    Inventors: Pedro B. Zanetta, Ricardo P. Coimbra
  • Patent number: 10205423
    Abstract: A source follower method, system, and apparatus provide rail-to-rail capability to an output voltage terminal of a voltage follower feedback biased CMOS output circuit by providing a control circuit which includes first and second bypass transistors that are connected in parallel between first and second control circuit input/output terminals and controlled, respectively, by first and second control circuit inputs, and which also includes first and second current sources for injecting source and sink currents in the output node as a function, respectively, of a first bypass current through the first bypass transistor which turns ON when the output voltage rises above a top threshold voltage level and of a second bypass current through the second bypass transistor which turns ON when the output voltage falls below a bottom threshold voltage level.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: February 12, 2019
    Assignee: NXP USA, Inc.
    Inventors: Pedro B. Zanetta, Ricardo P. Coimbra
  • Patent number: 9310261
    Abstract: A die temperature measurement system (300) includes an external test environment setup (352) and an integrated circuit (302). The external test environment setup (352) includes means to force and accurately measure electrical variables. The integrated circuit (302) includes a bipolar transistor (325); a selectable switch (340) for selecting from plurality of integrated resistances (342, 344) to be coupled in series between a base (322) of the bipolar transistor and a first input (362); and a selectable-gain current mirror (310) with a gain, a programmable current-mirror output coupled to the collector (326) of the bipolar transistor. The bipolar transistor and optional diodes (335) are sequentially biased with a set of proportional collector current levels. For each bias condition, the temperature-dependent voltage produced by the structure is extracted and stored. Die temperature is obtained through algebraic manipulation (450) of this data. Parasitic resistance and I/O pad leakage effects are canceled.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: April 12, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ricardo P. Coimbra, Edevaldo Pereira Da Silva, Jr., Pedro B. Zanetta
  • Patent number: 9074943
    Abstract: A die temperature measurement system (300) includes an external test environment setup (352) and an integrated circuit (302). The external test environment setup (352) includes means to force and accurately measure electrical variables. The integrated circuit (302) includes a bipolar transistor (325); a selectable switch (340) for selecting from plurality of integrated resistances (342, 344) to be coupled in series between a base (322) of the bipolar transistor and a first input (362); and a selectable-gain current mirror (310) with a gain, a programmable current-mirror output coupled to the collector (326) of the bipolar transistor. The bipolar transistor and optional diodes (335) are sequentially biased with a set of proportional collector current levels. For each bias condition, the temperature-dependent voltage produced by the structure is extracted and stored. Die temperature is obtained through algebraic manipulation (450) of this data. Parasitic resistance and I/O pad leakage effects are canceled.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: July 7, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ricardo Pureza Coimbra, Edevaldo Pereira da Silva, Jr., Pedro B. Zanetta
  • Publication number: 20150177075
    Abstract: A die temperature measurement system (300) includes an external test environment setup (352) and an integrated circuit (302). The external test environment setup (352) includes means to force and accurately measure electrical variables. The integrated circuit (302) includes a bipolar transistor (325); a selectable switch (340) for selecting from plurality of integrated resistances (342, 344) to be coupled in series between a base (322) of the bipolar transistor and a first input (362); and a selectable-gain current mirror (310) with a gain, a programmable current-mirror output coupled to the collector (326) of the bipolar transistor. The bipolar transistor and optional diodes (335) are sequentially biased with a set of proportional collector current levels. For each bias condition, the temperature-dependent voltage produced by the structure is extracted and stored. Die temperature is obtained through algebraic manipulation (450) of this data. Parasitic resistance and I/O pad leakage effects are canceled.
    Type: Application
    Filed: March 6, 2015
    Publication date: June 25, 2015
    Inventors: RICARDO P. COIMBRA, EDEVALDO PEREIRA DA SILVA, JR., PEDRO B. ZANETTA