Abstract: In a data processing system, the subject error correcting circuit is connected in the bridging mode to the data bus which interconnects a processor and a memory for error detection. It is presumed that the memory words obtained from the memory are relatively error-free, and the subject circuit does not delay their transmission, but simply monitors the data. If an error in the data is detected, an error signal is generated on the next processor microcycle, the processor aborts its present operation and then fetches the corrected data from the error correction circuit. If the frequency of errors increases or if a permanent error is detected, the subject error correction circuit switches to an in-line mode where it functions much as prior art error correction circuits: delaying the transmission of each memory word until the error check is complete.

Abstract: A microprocessor system that provides protection against memory violations by interrupting the central processing unit (CPU). A problem arises when the interrupt itself causes memory violations in push-down stack operations. This problem is solved by providing an auxiliary memory to store stack overflow data. Memory violations are detected (30, 40) and overflow data is written (42, 60, 33, 100) into auxiliary memory, at sequential locations (50, 51, 60). An interrupt signal is returned (30, 20) to the CPU. A stack overflow interrupt program reads the number of locations written (50, 80, 90), and accesses the auxiliary memory (100, 60, 70, 90) to determine and correct the cause of the overflow.