Patents by Inventor Pedro Ovalle
Pedro Ovalle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11824536Abstract: An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.Type: GrantFiled: February 22, 2023Date of Patent: November 21, 2023Assignee: Microchip Technology IncorporatedInventors: Yong Yuenyongsgool, Stephen Bowling, Pedro Ovalle
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Publication number: 20230308084Abstract: An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.Type: ApplicationFiled: February 22, 2023Publication date: September 28, 2023Applicant: Microchip Technology IncorporatedInventors: Yong Yuenyongsgool, Stephen Bowing, Pedro Ovalle
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Patent number: 11621702Abstract: An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.Type: GrantFiled: December 21, 2021Date of Patent: April 4, 2023Assignee: Microchip Technology IncorporatedInventors: Yong Yuenyongsgool, Stephen Bowling, Pedro Ovalle
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Publication number: 20220302904Abstract: An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.Type: ApplicationFiled: December 21, 2021Publication date: September 22, 2022Applicant: Microchip Technology IncorporatedInventors: Yong Yuenyongsgool, Stephen Bowling, Pedro Ovalle
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Patent number: 8533522Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: GrantFiled: September 21, 2012Date of Patent: September 10, 2013Assignee: MOSAID Technologies IncorporatedInventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Patent number: 8296598Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: GrantFiled: May 23, 2011Date of Patent: October 23, 2012Assignee: Mosaid Technologies IncorporatedInventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Patent number: 8069363Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: GrantFiled: August 19, 2009Date of Patent: November 29, 2011Assignee: Mosaid Technologies IncorporatedInventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Publication number: 20110228626Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: ApplicationFiled: May 23, 2011Publication date: September 22, 2011Inventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Publication number: 20100033216Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: ApplicationFiled: August 19, 2009Publication date: February 11, 2010Applicant: MOSAID Technologies IncorporatedInventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Patent number: 7596710Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: GrantFiled: December 14, 2005Date of Patent: September 29, 2009Assignee: MOSAID Technologies IncorporatedInventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Publication number: 20060103439Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: ApplicationFiled: December 14, 2005Publication date: May 18, 2006Inventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Patent number: 7010713Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: GrantFiled: January 27, 2003Date of Patent: March 7, 2006Assignee: MOSAID Technologies, Inc.Inventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Publication number: 20040123175Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: ApplicationFiled: January 27, 2003Publication date: June 24, 2004Applicant: MOSAID Technologies, Inc.Inventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Patent number: 6313664Abstract: A primary driver is activated to drive an output signal in response to an input signal. A reference signal is generated in response to the input signal. The output signal is compared to the reference signal. When the output signal lags the reference signal by a predefined amount an auxiliary driver is activated.Type: GrantFiled: March 20, 2000Date of Patent: November 6, 2001Assignee: Motorola Inc.Inventors: Geoffrey B. Hall, Pedro Ovalle, Dzung T. Tran
