Patents by Inventor Pei-Cheng Fan
Pei-Cheng Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881446Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.Type: GrantFiled: December 23, 2021Date of Patent: January 23, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Pei Cheng Fan
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Publication number: 20230361013Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.Type: ApplicationFiled: July 3, 2023Publication date: November 9, 2023Inventor: PEI CHENG FAN
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Patent number: 11764108Abstract: The present disclosure provides a method for preparing a semiconductor die structure with air gaps for reducing capacitive coupling between conductive features and a method for preparing the semiconductor die structure. The method includes: forming a first supporting backbone on the substrate; forming a first conductor block on the first supporting backbone; forming a second supporting backbone on the substrate; forming a second conductor block on the second supporting backbone; forming a third conductor block suspended above the substrate and connected to the first conductor block and the second conductor block; sequentially forming an energy removable layer and a capping dielectric layer over the substrate, and the energy removable layer and the capping dielectric layer separating the first conductor block, the second conductor block and the third conductor block; and performing a heat treatment process to transform the energy removable layer into a plurality of air gap structures.Type: GrantFiled: November 2, 2021Date of Patent: September 19, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Pei-Cheng Fan
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Publication number: 20230207433Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of middle interconnectors positioned between the first side of the package structure and the first die and between the first side of the package structure and the second die. The plurality of middle interconnectors respectively includes a middle exterior layer positioned between the first side of the package structure and the interposer structure, a middle interior layer enclosed by the middle exterior layer, and a cavity enclosed by the interposer structure, the package structure, and the middle interior layer.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventor: PEI CHENG FAN
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Publication number: 20230187464Abstract: The present application discloses an optical semiconductor device. The optical semiconductor device includes a logic die including a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and including a memory cell area and a memory peripheral area, and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via, and a second intra-die via positioned in the sensor peripheral area. A height of the first intra-die via is greater than a height of the second intra-die via.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Inventor: PEI CHENG FAN
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Patent number: 11605540Abstract: The present disclosure provides a method for preparing a semiconductor device structure with fine boron nitride spacer patterns. The method includes undercutting a photoresist pattern over a semiconductor substrate, and forming an inner spacer element over a sidewall surface of the photoresist pattern. The inner spacer element has a portion extending into a recess (i.e., the undercut region) of the photoresist pattern to form a footing, and a width of the portion of the inner spacer element increases continuously as the portion extends toward the semiconductor substrate. As a result, the inner spacer element may be prevented from collapsing after removal of the photoresist pattern.Type: GrantFiled: March 23, 2022Date of Patent: March 14, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Pei Cheng Fan
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Patent number: 11462406Abstract: The present disclosure provides a semiconductor device structure with fine boron nitride spacer patterns and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first boron nitride spacer disposed over the first target structure, wherein a topmost point of the first boron nitride spacer is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.Type: GrantFiled: July 29, 2020Date of Patent: October 4, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Pei Cheng Fan
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Publication number: 20220216054Abstract: The present disclosure provides a method for preparing a semiconductor device structure with fine boron nitride spacer patterns. The method includes undercutting a photoresist pattern over a semiconductor substrate, and forming an inner spacer element over a sidewall surface of the photoresist pattern. The inner spacer element has a portion extending into a recess (i.e., the undercut region) of the photoresist pattern to form a footing, and a width of the portion of the inner spacer element increases continuously as the portion extends toward the semiconductor substrate. As a result, the inner spacer element may be prevented from collapsing after removal of the photoresist pattern.Type: ApplicationFiled: March 23, 2022Publication date: July 7, 2022Inventor: PEI CHENG FAN
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Patent number: 11270908Abstract: The present disclosure provides a semiconductor die structure with air gaps for reducing capacitive coupling between conductive features and a method for preparing the semiconductor die structure. The semiconductor die structure includes a substrate; a first supporting backbone disposed on the substrate; a second supporting backbone disposed on the substrate; a first conductor block disposed on the first supporting backbone; a second conductor block disposed on the second supporting backbone; a third conductor block disposed above the substrate and connected to the first conductor block and the second conductor block; and an air gap structure disposed between the first conductor block, the second conductor block, and the third conductor block, wherein the air gap structure comprises an air gap and a liner layer enclosing the air gap.Type: GrantFiled: April 22, 2020Date of Patent: March 8, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Pei-Cheng Fan
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Publication number: 20220059399Abstract: The present disclosure provides a method for preparing a semiconductor die structure with air gaps for reducing capacitive coupling between conductive features and a method for preparing the semiconductor die structure. The method includes: forming a first supporting backbone on the substrate; forming a first conductor block on the first supporting backbone; forming a second supporting backbone on the substrate; forming a second conductor block on the second supporting backbone; forming a third conductor block suspended above the substrate and connected to the first conductor block and the second conductor block; sequentially forming an energy removable layer and a capping dielectric layer over the substrate, and the energy removable layer and the capping dielectric layer separating the first conductor block, the second conductor block and the third conductor block; and performing a heat treatment process to transform the energy removable layer into a plurality of air gap structures.Type: ApplicationFiled: November 2, 2021Publication date: February 24, 2022Inventor: PEI-CHENG FAN
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Publication number: 20220037155Abstract: The present disclosure provides a semiconductor device structure with fine boron nitride spacer patterns and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first boron nitride spacer disposed over the first target structure, wherein a topmost point of the first boron nitride spacer is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.Type: ApplicationFiled: July 29, 2020Publication date: February 3, 2022Inventor: PEI-CHENG FAN
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Publication number: 20210335653Abstract: The present disclosure provides a semiconductor die structure with air gaps for reducing capacitive coupling between conductive features and a method for preparing the semiconductor die structure. The semiconductor die structure includes a substrate; a first supporting backbone disposed on the substrate; a second supporting backbone disposed on the substrate; a first conductor block disposed on the first supporting backbone; a second conductor block disposed on the second supporting backbone; a third conductor block disposed above the substrate and connected to the first conductor block and the second conductor block; and an air gap structure disposed between the first conductor block, the second conductor block, and the third conductor block, wherein the air gap structure comprises an air gap and a liner layer enclosing the air gap.Type: ApplicationFiled: April 22, 2020Publication date: October 28, 2021Inventor: Pei-Cheng FAN
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Patent number: 9069253Abstract: A mask structure, including a substrate; an absorber layer formed on the substrate; and a patterned reflection layer formed on the absorber layer. Optionally, the mask structure may further include a buffer layer, a conductive coating, or combinations thereof. The buffer layer may be formed between the absorber layer and the reflection layer, and the conductive coating may be formed at a back side of the substrate.Type: GrantFiled: March 13, 2013Date of Patent: June 30, 2015Assignee: Nanya Technology CorportionInventors: Yu-Mei Ni, Chun-Yen Huang, Pei-Cheng Fan
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Publication number: 20140272674Abstract: A mask structure, including a substrate; an absorber layer formed on the substrate; and a patterned reflection layer formed on the absorber layer. Optionally, the mask structure may further include a buffer layer, a conductive coating, or combinations thereof. The buffer layer may be formed between the absorber layer and the reflection layer, and the conductive coating may be formed at a back side of the substrate.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: NANYA TECHNOLOGY CORP.Inventors: Yu-Mei Ni, Chun-Yen Huang, Pei-Cheng Fan
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Publication number: 20120244459Abstract: A mask for evaluating overlay error comprises a plurality of replicate device regions and an overlay mark. The plurality of replicate device regions are disposed uniformly on the mask, wherein each comprises a plurality of device patterns; and a plurality of current layer check patterns are formed adjacent to the plurality of device patterns. The overlay mark is formed on the corner of the mask's peripheral region. In particular, the current layer check patterns are configured to evaluate the pattern offset of a current mask, and the overlay mark and the current layer check patterns are configured to evaluate the overlay error by performing an exposure process using the current mask and a next mask.Type: ApplicationFiled: March 24, 2011Publication date: September 27, 2012Applicant: NANYA TECHNOLOGY CORP.Inventors: Kuan Ting CHOU, Pei Cheng FAN
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Patent number: 7651824Abstract: A method for compensating critical dimension (CD) variations of patterns of a substrate, by the correcting the CD of the corresponding photomask is disclosed. First, a light and a main photomask are provided. Second, an auxiliary photomask including an auxiliary transparent substrate and a shading element within the auxiliary transparent substrate is provided. Next the light passes through the auxiliary photomask and main photomask in order for compensating CD variations of patterns corresponding to main photomask.Type: GrantFiled: December 7, 2008Date of Patent: January 26, 2010Assignee: Nanya Technology Corp.Inventors: Hsuan-Ko Chen, Mei-Li Wang, Chih-Cheng Chin, Pei-Cheng Fan