Patents by Inventor Pei-Chia Chiang
Pei-Chia Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8605493Abstract: A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.Type: GrantFiled: May 22, 2012Date of Patent: December 10, 2013Assignee: Higgs Opl. Capital LLCInventors: Shyh-Shyuan Sheu, Pei-Chia Chiang, Wen-Pin Lin
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Patent number: 8392132Abstract: A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result.Type: GrantFiled: August 5, 2010Date of Patent: March 5, 2013Assignee: Industrial Technology Research InstituteInventors: Ku-Feng Lin, Meng-Fan Chang, Shyh-Shyuan Sheu, Pei-Chia Chiang, Wen-Pin Lin, Chih-He Lin
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Patent number: 8300449Abstract: A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.Type: GrantFiled: November 29, 2010Date of Patent: October 30, 2012Assignee: Industrial Technology Research InstituteInventors: Chih-He Lin, Shyh-Shyuan Sheu, Wen-Pin Lin, Pei-Chia Chiang
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Patent number: 8218361Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.Type: GrantFiled: August 23, 2011Date of Patent: July 10, 2012Assignee: Nanya Technology CorporationInventors: Shyh-Shyuan Sheu, Lieh-Chiu Lin, Pei-Chia Chiang, Wen-Pin Lin
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Patent number: 8199561Abstract: A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.Type: GrantFiled: September 21, 2009Date of Patent: June 12, 2012Assignee: Higgs OPL. Capital LLCInventors: Shyh-Shyuan Sheu, Pei-Chia Chiang, Wen-Pin Lin
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Publication number: 20120075908Abstract: A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.Type: ApplicationFiled: November 29, 2010Publication date: March 29, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-He Lin, Shyh-Shyuan Sheu, Wen-Pin Lin, Pei-Chia Chiang
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Publication number: 20110317483Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.Type: ApplicationFiled: August 23, 2011Publication date: December 29, 2011Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Shyh-Shyuan Sheu, Lieh-Chiu Lin, Pei-Chia Chiang, Wen-Pin Lin
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Publication number: 20110270555Abstract: A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result.Type: ApplicationFiled: August 5, 2010Publication date: November 3, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ku-Feng Lin, Meng-Fan Chang, Shyh-Shyuan Sheu, Pei-Chia Chiang, Wen-Pin Lin, Chih-He Lin
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Patent number: 8040723Abstract: A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.Type: GrantFiled: December 31, 2009Date of Patent: October 18, 2011Assignee: Industrial Technology Research InstituteInventors: Shyh-Shyuan Sheu, Pei-Chia Chiang, Wen-Pin Lin, Chih-He Lin
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Patent number: 8031515Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.Type: GrantFiled: November 21, 2008Date of Patent: October 4, 2011Assignee: Nanya Technology Corp.Inventors: Shyh-Shyuan Sheu, Lieh-Chiu Lin, Pei-Chia Chiang, Wen-Pin Lin
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Patent number: 8014194Abstract: A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change storage element, a bit select switch, a pulse generating module, and a counting module. The switching circuit comprises a plurality of switches, selectively providing branch paths to an output terminal of a current source. The bit select switch controls the conduction between the phase change storage element and the output terminal of the current source. The pulse generating module outputs a pulse signal oscillating between high and low voltage levels. When enabled, the counting module counts the oscillations of the pulse signal, and outputs the count result by a set of digital data. The set of digital data are coupled to the switching circuit to control the switches therein.Type: GrantFiled: September 16, 2009Date of Patent: September 6, 2011Assignees: Nanya Technology Corporation, Winbond Electronics CorpInventors: Shyh-Shyuan Sheu, Pei-Chia Chiang, Wen-Pin Lin
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Patent number: 7974122Abstract: A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state.Type: GrantFiled: June 16, 2009Date of Patent: July 5, 2011Assignee: Industrial Technology Research InstituteInventors: Wen-Pin Lin, Shyh-Shyuan Sheu, Pei-Chia Chiang
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Publication number: 20110122684Abstract: A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.Type: ApplicationFiled: December 31, 2009Publication date: May 26, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Shyh-Shyuan Sheu, Pei-Chia Chiang, Wen-Pin Lin, Chih-He Lin
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Patent number: 7933147Abstract: A sensing circuit of a phase change memory. The sensing circuit comprises a data current source and a reference current source, a storage memory device and a reference memory device, a storage switch and a reference switch, an auxiliary current source and a comparator. First terminals of the storage memory device and the reference memory device are respectively coupled to the data current source and the reference current source. The storage switch and the reference switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The auxiliary current source is dynamically coupled to the first terminals of the storage memory device and the reference memory device. The comparator is coupled to the first terminals of the storage memory device and the reference memory device.Type: GrantFiled: December 31, 2007Date of Patent: April 26, 2011Assignee: Industrial Technology Research InstituteInventors: Lieh-Chiu Lin, Shyh-Shyuan Sheu, Pei-Chia Chiang
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Patent number: 7889547Abstract: A memory having a memory cell, a resistance estimator and a write current generator. The resistance estimator is coupled to the memory cell to estimate the resistance of the memory cell and outputs an estimated resistance level. According to the estimated resistance level, the write current generator generates a write current to flow through the memory cell and to change the resistance of the memory cell. The write current is in a pulse form, and the write current generator sets the pulse width, or magnitude, or both the pulse width and the magnitude of the write current according to the estimated resistance level.Type: GrantFiled: December 29, 2008Date of Patent: February 15, 2011Assignee: Industrial Technology Research InstituteInventors: Shyh-Shyuan Sheu, Lieh-Chiu Lin, Pei-Chia Chiang, Wen-Pin Lin
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Patent number: 7885109Abstract: Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed.Type: GrantFiled: November 18, 2008Date of Patent: February 8, 2011Assignee: Industrial Technology Research InstituteInventors: Wen-Pin Lin, Shyh-Shyuan Sheu, Lieh-Chiu Lin, Pei-Chia Chiang
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Patent number: 7796454Abstract: A sensing circuit of a phase change memory. The sensing circuit comprises a storage capacitor and a reference capacitor, a storage memory device and a reference memory device, a storage discharge switch and a reference discharge switch, and an arbitrator. First terminals of the storage capacitor and the reference capacitor are respectively coupled to a pre-charge voltage via first switches. First terminals of the storage memory device and the reference memory device are respectively coupled to the first terminals of the storage capacitor and the reference capacitor. The storage discharge switch and the reference discharge switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The arbitrator is coupled to the first terminals of the storage memory device and the reference memory device and provides an output as a read result of the storage memory device.Type: GrantFiled: December 29, 2007Date of Patent: September 14, 2010Assignee: Industrial Technology Research InstituteInventors: Lieh-Chiu Lin, Shyh-Shyuan Sheu, Pei-Chia Chiang
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Patent number: 7796455Abstract: Devices controlling a phase change storage element and methods for increasing reliability of a phase change storage element. The invention introduces a first operation mode and a second operation mode. A reference phase change storage element is forced a write current for an ideal conduction period in the first operation mode. In the second operation mode, the invention generates a proper conduction period based on the resistance of the reference phase change storage element, and forces the write current into the controlled phase change storage element for the proper conduction period.Type: GrantFiled: June 19, 2008Date of Patent: September 14, 2010Assignee: Industrial Technology Research InstituteInventors: Pei-Chia Chiang, Shyh-Shyuan Sheu, Lieh-Chiu Lin, Wen-Pin Lin
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Patent number: RE45035Abstract: A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state.Type: GrantFiled: July 3, 2013Date of Patent: July 22, 2014Assignee: Higgs Opl. Capital LLCInventors: Wen-Pin Lin, Shyh-Shyuan Sheu, Pei-Chia Chiang
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Patent number: RE45189Abstract: An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched.Type: GrantFiled: August 10, 2012Date of Patent: October 14, 2014Assignee: Higgs OPL. Capital LLCInventors: Shyh-Shyuan Sheu, Lieh-Chiu Lin, Pei-Chia Chiang, Wen-Pin Lin