Patents by Inventor Pei-Hsuan Lee
Pei-Hsuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230417830Abstract: In a semiconductor manufacturing method includes providing a plurality of patterns on a semiconductor substrate. The patterns include an NMOS structure arranged next to an N+/N well structure, and/or a PMOS structure arranged next to a P+/P well structure. The method further includes: receiving a plurality of images by applying an electron beam to the patterns; and transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Inventors: Yu-Hsuan Huang, Chien-Liang Chen, Pei-Hsuan Lee
-
Publication number: 20230386013Abstract: The present disclosure provides a method and a system for scanning wafer. The system captures a defect image of a wafer, and generates a reference image corresponding to the first defect image based on a reference image generation model. The system generates a defect marked image based on the defect image and the reference image.Type: ApplicationFiled: July 27, 2023Publication date: November 30, 2023Inventors: PEI-HSUAN LEE, CHIEN-HSIANG HUANG, KUANG-SHING CHEN, KUAN-HSIN CHEN, CHUN-CHIEH CHIN
-
Patent number: 11830742Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: GrantFiled: June 29, 2022Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
-
Publication number: 20230378040Abstract: A package structure includes a carrier substrate, a die, and an encapsulant. The carrier substrate includes through carrier vias (TCV). The die is disposed over the carrier substrate. The die includes a semiconductor substrate and conductive posts disposed over the semiconductor substrate. The conductive posts face away from the carrier substrate. The encapsulant laterally encapsulates the die.Type: ApplicationFiled: July 27, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Yueh Wu, Chien-Ling Hwang, Jen-Chun Liao, Ching-Hua Hsieh, Pei-Hsuan Lee, Chia-Hung Liu
-
Publication number: 20230361039Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material.Type: ApplicationFiled: July 13, 2023Publication date: November 9, 2023Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
-
Patent number: 11791206Abstract: A method for forming a semiconductor device, includes: forming a metal layer on a semiconductor substrate; forming a dielectric layer over the metal layer; etching a top portion of the dielectric layer; after etching the top portion of the dielectric layer, removing first mist from a bottom portion of the dielectric layer; removing the bottom portion of the dielectric layer to expose the metal layer; performing a pre-clean operation, using an alcohol base vapor or an aldehyde base vapor, on the dielectric layer and the metal layer; and forming a conductor extending through the dielectric layer and in contact with the metal layer.Type: GrantFiled: July 27, 2020Date of Patent: October 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Tang Wu, Pao-Sheng Chen, Pei-Hsuan Lee, Szu-Hua Wu, Chih-Chien Chi
-
Patent number: 11783469Abstract: The present disclosure provides a method and a system for scanning wafer. The system captures a defect image of a wafer, and generates a reference image corresponding to the first defect image based on a reference image generation model. The system generates a defect marked image based on the defect image and the reference image.Type: GrantFiled: June 11, 2021Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Pei-Hsuan Lee, Chien-Hsiang Huang, Kuang-Shing Chen, Kuan-Hsin Chen, Chun-Chieh Chin
-
Patent number: 11756872Abstract: A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate.Type: GrantFiled: March 11, 2021Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Yueh Wu, Chien-Ling Hwang, Jen-Chun Liao, Ching-Hua Hsieh, Pei-Hsuan Lee, Chia-Hung Liu
-
Patent number: 11749582Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.Type: GrantFiled: July 27, 2022Date of Patent: September 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsiao-Chung Liang, Hao-Yi Tsai, Chien-Ling Hwang, Kuo-Lung Pan, Pei-Hsuan Lee, Tin-Hao Kuo, Chih-Hsuan Tai
-
Patent number: 11742290Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.Type: GrantFiled: April 28, 2021Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
-
Patent number: 11730816Abstract: The present invention relates to a modified starch and a method for obtaining the modified starch by using a debranching enzyme, such as isoamylase, pullulanase, limit dextrinase and the like. The debranching enzyme modified starch of present invention exhibits excellent film-forming capacity, film strength, and gelation ability, so as to be used as a material for making hard capsules without the use of coagulants and plasticizers.Type: GrantFiled: May 24, 2021Date of Patent: August 22, 2023Assignee: DAH FENG CAPSULE INDUSTRY CO., LTDInventors: Ruei-Jan Chang, Hsin-Yi Chao, Pei-Hsuan Lee, Wei-Yu Chen
-
Publication number: 20230121958Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.Type: ApplicationFiled: December 20, 2022Publication date: April 20, 2023Inventors: Hui Lee, Po-Hsiang Huang, Wen-Sheh Huang, Jen Hung Wang, Su-Jen Sung, Chih-Chien Chi, Pei-Hsuan Lee
-
Publication number: 20230103560Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.Type: ApplicationFiled: November 14, 2022Publication date: April 6, 2023Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
-
Patent number: 11538735Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.Type: GrantFiled: August 1, 2019Date of Patent: December 27, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Rong Chun, Kuo Lung Pan, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chen-Hua Yu
-
Patent number: 11532548Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.Type: GrantFiled: October 14, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hui Lee, Po-Hsiang Huang, Wen-Sheh Huang, Jen Hung Wang, Su-Jen Sung, Chih-Chien Chi, Pei-Hsuan Lee
-
Publication number: 20220367310Abstract: A package system and a manufacturing method thereof are provided. The package system includes a semiconductor package and a thermal-dissipating structure. The semiconductor package includes a first surface and a second surface opposing to each other, and a planarity of the second surface is greater than that of the first surface. The thermal-dissipating structure includes a first plate secured to the semiconductor package, a gasket interposed between the first plate and the semiconductor package, a second plate secured to the semiconductor package opposite to the first plate, and a first thermal interface material layer interposed between the second plate and the second surface of the semiconductor package. The gasket includes a plurality of hollow regions corresponding to portions of the first surface of the semiconductor package.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Hsuan Lee, Ching-Hua Hsieh, Chien-Ling Hwang
-
Patent number: 11502013Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.Type: GrantFiled: May 10, 2021Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
-
Publication number: 20220359343Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.Type: ApplicationFiled: July 27, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsiao-Chung Liang, Hao-Yi Tsai, Chien-Ling Hwang, Kuo-Lung Pan, Pei-Hsuan Lee, Tin-Hao Kuo, Chih-Hsuan Tai
-
Publication number: 20220359344Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.Type: ApplicationFiled: July 27, 2022Publication date: November 10, 2022Inventors: Shu-Rong Chun, Kuo-Lung Pan, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chen-Hua Yu
-
Publication number: 20220336367Abstract: A semiconductor device includes a source/drain component of a transistor. A source/drain contact is disposed over the source/drain component. A source/drain via is disposed over the source/drain contact. The source/drain via contains copper. A first liner at least partially surrounds the source/drain via. A second liner at least partially surrounds the first liner. The first liner and the second liner are disposed between the source/drain contact and the source/drain via. The first liner and the second liner have different material compositions.Type: ApplicationFiled: September 3, 2021Publication date: October 20, 2022Inventors: Chen-Hung Tsai, Chao-Hsun Wang, Pei-Hsuan Lee, Chih-Chien Chi, Ting-Kui Chang, Fu-Kai Yang, Mei-Yun Wang