Abstract: A semiconductor package structure includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a passivation layer on the semiconductor substrate and the conductive pad. The passivation layer exposes a portion of the top surface of the conductive pad. The semiconductor package structure also includes a conductive adhesive layer on the conductive pad, and a dielectric layer on the passivation layer and the conductive adhesive layer. The dielectric layer exposes a portion of the conductive adhesive layer. The semiconductor package structure also includes a redistribution layer (RDL) structure on the dielectric layer and electrically connected to the conductive pad through the conductive adhesive layer. The semiconductor package structure also includes a bump structure over the RDL structure.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.

Abstract: A distributed battery management system, for managing a plurality of battery management units, wherein each of the battery management units, includes: a first battery cell, forming a charge-discharge connection at least with a second battery cell in a second battery management unit; a monitor circuit, monitoring a discharge process of the first battery cell via the charge-discharge connection, to record a discharge voltage time history of the first battery cell; and a calculation unit, calculating a real-time maximal energy storage capacity of the first battery cell, by an electrochemical equation calculated based on the discharge voltage time history and an electrical current time history of the first battery cell during the discharge process. The history of the real-time maximal energy storage capacity of the battery cell may be stored as an identity resume of the battery cell, in a battery resume record device.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.

Abstract: A switch control unit and optical control unit, including: a digital-to-analog converter, being switchable between being coupled to a first sensing unit and being coupled to a drive unit, through a common contact pad; a sensing contact pad, coupled to a second sensing unit; an analog-to-digital converter, for sensing voltages at the contact pads when coupled to the sensing units, wherein each of the sensing units has a minimum working voltage level; and a loop switching unit, coupled between the common contact pad, the analog-to-digital converter, and the sensing contact pad, wherein when the voltage at the common contact pad is substantially higher than the minimum working voltage level, the loop switching unit conducts the common contact pad to the analog-to-digital converter to sense the voltage at the common contact pad, and the digital-to-analog converter enters a high-impedance state such that the digital-to-analog converter does not sense the voltage at the common contact pad.

Abstract: The present invention provides a differential signal offset adjustment circuit, wherein first and second transistors are respectively coupled between a power supply line and a first current source, and between the power supply line and a second current source. First and second resistors are respectively coupled between the first transistor and a first variable current source, and between the second transistor and a second variable current source. Third and fourth transistors are respectively coupled between a third resistor and a third current source, and between a fourth resistor and a fourth current source, and have input terminals respectively coupled to the first and second resistors. Fifth and sixth transistors are respectively coupled between the power supply line and a fifth current source, and between the power supply line and a sixth current source, and have input terminals respectively coupled to the third and fourth transistors.

Abstract: During frequency detection, a constant current source outputs an output current to charge a variable capacitor for multi-period. In a calibration mode, according to a comparison result between a cross voltage of the variable capacitor and a reference voltage, a capacitance value of the variable capacitor is adjusted. In a monitor mode, according to a reference frequency and the cross voltage of the variable capacitor, a frequency under test of a circuit under test is detected.

Abstract: When digital input data disappear temporarily, within a counting period of the counter and pulse generator, an output voltage of the voltage generator rises, a threshold detector compares the output voltage of the voltage generator with a plurality of threshold values to generate a plurality of comparison results, and a logic gate unit generates a control signal according to the comparison results, to a charge pump, so that the charge pump controls the voltage-controlled oscillator to accelerate or decelerate.

Abstract: When digital input data disappear temporarily, within a counting period of the counter and pulse generator, an output voltage of the voltage generator rises, a threshold detector compares the output voltage of the voltage generator with a plurality of threshold values to generate a plurality of comparison results, and a logic gate unit generates a control signal according to the comparison results, to a charge pump, so that the charge pump controls the voltage-controlled oscillator to accelerate or decelerate.

Abstract: The present invention provides a differential signal offset adjustment circuit, wherein first and second transistors are respectively coupled between a power supply line and a first current source, and between the power supply line and a second current source. First and second resistors are respectively coupled between the first transistor and a first variable current source, and between the second transistor and a second variable current source. Third and fourth transistors are respectively coupled between a third resistor and a third current source, and between a fourth resistor and a fourth current source, and have input terminals respectively coupled to the first and second resistors. Fifth and sixth transistors are respectively coupled between the power supply line and a fifth current source, and between the power supply line and a sixth current source, and have input terminals respectively coupled to the third and fourth transistors.

Abstract: During frequency detection, a constant current source outputs an output current to charge a variable capacitor for multi-period. In a calibration mode, according to a comparison result between a cross voltage of the variable capacitor and a reference voltage, a capacitance value of the variable capacitor is adjusted. In a monitor mode, according to a reference frequency and the cross voltage of the variable capacitor, a frequency under test of a circuit under test is detected.

Abstract: The present invention presents a DC bias circuit including a first biasing circuit and a second biasing circuit. The first biasing circuit includes a first biasing transistor and a first biasing resistor for providing a first bias voltage to an output transistor of the mixer circuit. The first biasing transistor and the output transistor are the same type of transistor and have equal channel lengths. The second biasing circuit includes a second biasing transistor and a second biasing resistor for providing a second bias voltage to an input transistor of the common gate amplifier circuit. The second biasing transistor and the input transistor are the same type of transistor and have equal channel lengths. When the input transistor and the output transistor all operate in a saturation region, alternating current signals output from the mixer circuit is unrelated to a threshold voltage of the output transistor.

Abstract: The present invention presents a DC bias circuit including a first biasing circuit and a second biasing circuit. The first biasing circuit includes a first biasing transistor and a first biasing resistor for providing a first bias voltage to an output transistor of the mixer circuit. The first biasing transistor and the output transistor are the same type of transistor and have equal channel lengths. The second biasing circuit includes a second biasing transistor and a second biasing resistor for providing a second bias voltage to an input transistor of the common gate amplifier circuit. The second biasing transistor and the input transistor are the same type of transistor and have equal channel lengths. When the input transistor and the output transistor all operate in a saturation region, alternating current signals output from the mixer circuit is unrelated to a threshold voltage of the output transistor.

Abstract: The present invention presents a RF receiver circuit including an inductor-coupling single-ended input differential-output LNA, a mixer circuit, and a differential trans-impedance amplifier. The inductor-coupling single-ended input differential-output LNA includes a single-ended input, a balance-to-unbalance transformer, and an inductor-less differential LNA. The balance-to-unbalance transformer is used to transform the radio frequency signals into a plurality of differential-output first differential signals and includes a first inductor and a second inductor.

Abstract: A frequency detection circuit includes a filter, a power detector and a voltage comparator. The filter receives and filters a converted signal to generate a filtered signal. The power of the filtered signal relates to a frequency of the converted signal. The power detector generates a voltage according to the power of the filtered signal. The voltage comparator compares the voltage with multiple reference voltages to generate multiple comparison results. At least one of the inductance and capacitance of an LC tank in an amplifier is adjusted according to the comparison results.

Abstract: An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.

Abstract: A frequency detection circuit includes a filter, a power detector and a voltage comparator. The filter receives and filters a converted signal to generate a filtered signal. The power of the filtered signal relates to a frequency of the converted signal. The power detector generates a voltage according to the power of the filtered signal. The voltage comparator compares the voltage with multiple reference voltages to generate multiple comparison results. At least one of the inductance and capacitance of an LC tank in an amplifier is adjusted according to the comparison results.

Abstract: An IC, a circuitry, and an RF BIST system are provided. The RF BIST system includes a test equipment, a module circuitry, and an IC. The IC is arranged to communicate with the module circuitry by an RF signal in response to a command signal from the test equipment, determine a test result by the RF signal, and report the test result to the test equipment, wherein the module circuitry is external to the IC and the test equipment.