Abstract: This application relates to compounds of Formula (I): or pharmaceutically acceptable salts thereof, which modulate the activity of adenosine receptors, such as subtypes A2A and A2B receptors, and are useful in the treatment of diseases related to the activity of adenosine receptors including, for example, cancer, inflammatory diseases, cardiovascular diseases, and neurodegenerative diseases.

Abstract: An ASIC chip for performing active battery equalization is provided. The ASIC chip for performing active battery equalization includes: a power conversion module, an equalization switch matrix circuit module comprising a power MOS transistor, a switch control module, a temperature protection module, and a communication interface module. By connecting and controlling the above modules, the equalization switch matrix circuit module performs equalization on a battery in the battery pack. That is, the use of the integrated ASIC chip accelerates and facilitates the BMS solution manufacturers adding the active equalization function, and facilitates the BMS Battery management system effectively improving the service performance and life of lithium batteries.

Abstract: The present disclosure provides the use of 4-(Phenylethynyl) benzoic acid in preparing a plant growth regulator. 4-(Phenylethynyl) benzoic acid has a formula as C15H10O2, a molecular weight of 222.2390. The optimum concentration of 4-(Phenylethynyl) benzoic acid in the plant growth regulator is in a range of 10 ?M to 200 ?M. The plant growth regulator further contains a pesticidally acceptable carrier. The present disclosure further provides the use of 4-(Phenylethynyl) benzoic acid in regulating plant growth. In the use of 4-(Phenylethynyl) benzoic acid in preparing a plant growth regulator of the present disclosure, 4-(Phenylethynyl) benzoic acid has the ABA-like effects, and is more stable, easily available, cheaper, and environmentally friendly. Therefore, the present disclosure is suitable for large-scale popularization.

Abstract: A method of estimating an optical flow includes processing, using an image processing pass, a first image and a second image separately, and estimating the optical flow based on a second image attention feature map of the first image and a second image attention feature map of the second image. The processing using the image processing pass includes extracting a feature map by encoding an image, outputting a first image fusion attention feature map by fusing row relationship information of the image with the image feature map, outputting a first image attention feature map of the image based on the first image fusion attention feature map and the image feature map, outputting a second image fusion attention feature map by fusing column relationship information of the image with the first image attention feature map, and generating a second image attention feature map of the image based on the second image fusion attention feature map and the first image attention feature map.

Abstract: Disclosed is a method for identifying fragile lines in power grid based on electrical betweenness, which comprises the following steps: constructing the power grid into a network diagram, sequentially removing lines in the network diagram, and sorting the electrical betweenness of each line from large to small; constructing a nonlinear model of complex network cascade failure considering overload and weighted edges, and respectively performing two ways of removing lines for sorted electrical betweenness, namely sequentially removing preset proportion lines and sequentially removing all lines until no new lines are removed in the network diagram; obtaining a change of generator-load power before and after each line removal, and evaluating a severity of power grid failure based on the change of generator-load power, thus completing an identification of power grid fragile lines.

Abstract: Provided are a wireless power apparatus, a charging dock and an electronic equipment. In the wireless power apparatus, a housing is provided with a mounting cavity; a first battery is disposed within the mounting cavity; multiple first magnetic pieces are disposed in the housing and are configured for adsorbing multiple first adsorption pieces of an equipment body, respectively; a first charging assembly is configured to charge the first battery, a wireless power supply assembly is disposed within the mounting cavity, is electrically connected to the first battery, and is capable of transmitting power of the first battery to the equipment body.

Abstract: A wafer processing system and a rework method thereof are provided. An image capture device captures an image of a wafer to generate a captured image. A control device detects a defect pattern in the captured image, calculates a target removal thickness according to distribution of contrast values of the defect pattern, and controls a processing device to perform processing on the wafer according to the target removal thickness.

Abstract: The invention discloses a method, a system, a device, and a medium for detecting a battery state of health. The method includes extracting a target curve segment from a first charging characteristic curve of a battery under test; and determining, according to a corresponding relation between characteristic parameters of the target curve segment and the battery state of health, the battery state of health matching the characteristic parameters of the target curve segment, and determining the battery state of health as the battery state of health of the battery under test. By utilizing said corresponding relation as the calculation basis, the invention improves the reliability and accuracy of the detection of battery state of health detection. The invention also tracks instances of abusive conditions that accelerate battery aging, assessing whether such conditions accelerate battery degradation and issuing warnings accordingly.

Abstract: The invention discloses a method, a system, an electronic device, and a storage medium for determining performance of a power battery. The method includes the following steps: acquiring historical data of the power battery in at least two charging processes; determining, according to historical data in one charging process, a dQ/dV curve and a direct current internal resistance corresponding to said charging process; calculating a relative change rate of internal resistance capacity in any two charging processes; and determining the performance of the power battery according to the relative change rate of internal resistance capacity and a relative change rate of internal resistance capacity range corresponding to fault type. The invention can effectively determine whether the performance of the power battery is abnormal by combining, in the two charging processes, the target peak value of a dQ/dV curve of the power battery and the change in direct current internal resistance.

Abstract: A computer system includes a first computing node and a second computing node. The first computing node includes a first device and a first memory. The second computing node includes a second device and a second memory. The first memory includes a first memory space. The second memory includes a second memory space. The first device obtains a cross-node read instruction. The cross-node read instruction includes a virtual address of the second memory space and a size of first data. The first device determines an identifier (ID) of the second computing node based on the virtual address of the second memory space and a first correspondence, to obtain a first network transmission packet, and sends the packet to the second device. The second device receives the packet, reads the first data from the second memory space, and sends the first data to the first device.

Abstract: A data prefetch method is disclosed. Before data is prefetched, a first data access request is first obtained, and a data prefetch policy is determined based on the first data access request and a data lifecycle, so that a first data set stored in a second storage medium is stored into a first storage medium according to the data prefetch policy. The first data set includes at least one piece of data, the data prefetch policy includes at least a prefetch length, the data lifecycle indicates duration for storing data in the first storage medium, and a read/write access rate of the second storage medium is less than that of the first storage medium.

Abstract: This application describes methods of inhibiting APOL1 and treating APOL1-mediated kidney diseases comprising administering Compound I and/or a pharmaceutically acceptable salt thereof. The application also describes pharmaceutical compositions comprising Compound I and/or a pharmaceutically acceptable salt thereof.

Abstract: A method, device, and system for controlling a data read/write command in an NVMe over fabric architecture. In the method provided in the embodiments of the present disclosure, a data processing unit receives a control command sent by a control device, the data processing unit divides a storage space of a buffer unit into at least two storage spaces according to the control command sent by the control device, and establishes a correspondence between the at least two storage spaces and command queues, and after receiving a first data read/write command that is in a first command queue and that is sent by the control device, the data processing unit buffers, in a storage space that is of the buffer unit and that is corresponding to the first command queue, data to be transmitted according to the first data read/write command.

Abstract: The present invention relates to IRAKIMiD degraders, their liquid formulations, and methods of use thereof for treating cancer.

Abstract: A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.

Abstract: A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.

Abstract: The invention provides a light spot scanning device, a scanning method thereof, and a medical cosmetology device, belonging to the technical field of medical cosmetology, comprising a laser and a collimating lens and a reflector arranged in sequence along the optical path transmission direction of the laser. The reflector is also connected with a driving member, the laser beam emitted by the laser forms a linear light spot through the collimating lens, and the reflector is driven to continuously rotate according to a preset path through the driving member. A plurality of linear light spots formed by the continuous rotation are sequentially overlapped on the light exiting side of the reflector to form a scanning linear light spot. Each time the reflector rotates, a group of linear light spots is formed. After continuous rotation, multiple groups of sequentially overlapping linear light spots are formed on the light exiting side of the reflector, called scanning linear light spots.

Abstract: Example data transmission methods, processor systems, and memory access systems are provided. One example processor system is applied to a source end device. The processor system includes a processor core and a first remote direct memory access (RDMA) network interface card. The processor core is configured to deliver a memory write instruction. The memory write instruction includes to-be-written data and a destination address of the to-be-written data. The destination address is a memory address of a destination end device. The first RDMA network interface card is configured to encapsulate the to-be-written data based on the destination address of the to-be-written data and configuration information of the destination end device and send the encapsulated to-be-written data to a second RDMA network interface card of the destination end device.

Abstract: A high writing rate antifuse array includes at least one sub-memory array including two antifuse memory cells arranged side by side between two neighboring bit lines. Each of two antifuse memory cells includes an antifuse transistor. The antifuse transistor has at least one sharp corner overlapping an antifuse gate above a first gate dielectric layer. Each of two antifuse memory cells includes a selection transistor. The second gate dielectric layers of two selection transistors are connected with each other. Thus, two antifuse memory cells are connected with the same select line and the same word line but are respectively connected with different bit lines. In the present invention, a common source contact is used, and two selection transistors share a channel, whereby to stabilize the source structure, increase the channel width of the selection transistors, and raise the writing rate without increase of overall area of the layout.