Abstract: A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: The invention provides a material for contact lenses, including a first siloxane macromer shown as formula (I): in formula (I), R1, R2 and R3 are C1-C4 alkyl groups, R4 is C1-C6 alkyl group, R5 is C1-C4 alkylene group, R6 is —OR7O— or —NH—, R7 and R8 are C1-C4 alkylene groups and m is an integer of about 1-2, n is an integer of about 4-80; a second siloxane macromer shown as formula (II): in formula (II), R9, R10 and R11 are C1-C4 alkyl groups, R12, R13 and R15 are C1-C3 alkylene group, R14 is a residue obtained by removing NCO group from an aliphatic or aromatic diisocyanate, and o is an integer of about 4-80, p is an integer of about 0-1; q is an integer of about 1-20; at least one hydrophilic monomer and an initiator.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

Abstract: A scheduling method of uplink resource unit includes selecting an uplink parameter set, by calculating the uplink parameter set capable of achieving a minimized energy consumption according to a traffic and a QoS of a user equipment (UE). The uplink parameter set allows a plurality of transmission variations. A score function is used to calculate a score of a transmission condition variation of the UE and a transmission order of the UE is determined according to the score. A disposing position of the resource units in uplink subcarriers is determined. The time occupied by the disposing position is checked to see whether or a delay constraint allowed by the UE is satisfied. If the result of checking the disposing position does not satisfy the delay constraint, the number of consecutive subcarriers is changed and the step of determining the disposing position of the resource units in the uplink subcarriers is repeatedly performed.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: A scheduling method of uplink resource unit includes selecting an uplink parameter set, by calculating the uplink parameter set capable of achieving a minimized energy consumption according to a traffic and a QoS of a user equipment (UE). The uplink parameter set allows a plurality of transmission variations. A score function is used to calculate a score of a transmission condition variation of the UE and a transmission order of the UE is determined according to the score. A disposing position of the resource units in uplink subcarriers is determined. The time occupied by the disposing position is checked to see whether or a delay constraint allowed by the UE is satisfied. If the result of checking the disposing position does not satisfy the delay constraint, the number of consecutive subcarriers is changed and the step of determining the disposing position of the resource units in the uplink subcarriers is repeatedly performed.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: The invention provides a material including a first siloxane macromer shown as formula (I): in which R1, R2 and R3 are C1-C4 alkyl groups, R4 is C1-C6 alkyl group, R5 is C1-C4 alkylene group, R6 is —OR7O— or —NH—, R7 and R8 are C1-C4 alkylene groups and m is an integer of 1-2, n is an integer of 4-80; a second siloxane macromer shown as formula (II): in which R9, R10 and R11 are C1-C4 alkyl groups, R12, R13 and R15 are C1-C3 alkylene group, R14 is a residue obtained by removing NCO group from an aliphatic or aromatic diisocyanate, and o is an integer of 4-80, p is an integer of 0-1; q is an integer of about 1-20; at least one hydrophilic monomer and an initiator.

Abstract: The invention provides a material for contact lenses, including a first siloxane macromer shown as formula (I): in formula (I), R1, R2 and R3 are C1-C4 alkyl groups, R4 is C1-C6 alkyl group, R5 is C1-C4 alkylene group, R6 is —OR7O— or —NH—, R7 and R8 are C1-C4 alkylene groups and m is an integer of about 1-2, n is an integer of about 4-80; a second siloxane macromer shown as formula (II): in formula (II), R9, R10 and R11 are C1-C4 alkyl groups, R12, R13 and R15 are C1-C3 alkylene group, R14 is a residue obtained by removing NCO group from an aliphatic or aromatic diisocyanate, and o is an integer of about 4-80, p is an integer of about 0-1; q is an integer of about 1-20; at least one hydrophilic monomer and an initiator.

Abstract: The invention provides a material for contact lenses, including a first siloxane macromer shown as formula (I): in formula (I), R1, R2 and R3 are C1-C4 alkyl groups, R4 is C1-C6 alkyl group, R5 is C1-C4 alkylene group, R6 is —OR7O— or —NH—, R7 and R8 are C1-C4 alkylene groups and m is an integer of about 1-2, n is an integer of about 4-80; a second siloxane macromer shown as formula (II): in formula (II), R9, R10 and R11 are C1-C4 alkyl groups, R12, R13 and R15 are C1-C3 alkylene group, R14 is a residue obtained by removing NCO group from an aliphatic or aromatic diisocyanate, and o is an integer of about 4-80, p is an integer of about 0-1; q is an integer of about 1-20; at least one hydrophilic monomer and an initiator.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.