Abstract: An electrode structure for a front board of a plasma display panel (PDP). The electronic structure connects all the sustain electrodes on the front board to prevent data transformation errors caused by holes. The fabrication method of the electronic structure is also disclosed.

Abstract: An electrode structure for a front board of a plasma display panel (PDP). The electronic structure connects all the sustain electrodes on the front board to prevent data transformation errors caused by holes. The fabrication method of the electronic structure is also disclosed.

Abstract: A method for on-chip polishing pad conditioning in a chemical mechanical polishing process is disclosed. In the method, a plurality of dummy patterns in a designated area on a wafer surface are planted during the same photolithographic method for forming the IC dies. The designated area may be the edge portion, i.e., the blanket area along the edges of a wafer, or the scribe lines formed on the wafer. The dummy patterns should be formed to a step height of at least 2,000 Å, and preferably to at least 4,000 Å. The present invention plurality of dummy patterns is used during a polishing process for the top surface of a semiconductor wafer by a polishing pad. The plurality of dummy patterns simultaneously conditions the pad in a localized manner to improve the removal rate of the pad. The shape of the dummy patterns can be formed in any desirable shape, including those that have a cross-section of a square or a rectangle with a width of at least 100 Å.