Abstract: A manufacturing method for a package substrate, the method including: forming a package substrate by a first dielectric layer formed by weaving at least fiberglass of a first width and a second dielectric layer formed by weaving at least fiberglass of a second width. The second width is different from the first width, and the weaving direction of the fiberglass in the first dielectric layer is 90° relative to the weaving direction of the fiberglass in the second dielectric layer.

Abstract: The present disclosure provides a package substrate structure and a method for manufacturing the same. The method includes: providing a substrate, forming a first hole with a first radial dimension in the substrate; forming a first metal layer on the sidewall of the first via to form a first via; filing the first via with a dielectric layer; forming a second hole with a second radial dimension in the dielectric layer, wherein the second radial dimension is smaller than the first radial dimension, and the second hole and the first metal layer are separated by the dielectric layer; filling the second hole with the second metal layer to form a second via. The high-speed circuit via design achieved by a sleeve via arrangement of the present disclosure can reduce the influence of the impedance mismatch caused by vias on insertion loss and the return loss in a specific frequency band.

Abstract: A method for manufacturing an electrical performance test structure of packaged chip, and a method for testing electrical performance of packaged chip, including: providing a first wafer and a second wafer, forming a top metal layer on the first wafer and the second wafer respectively, forming bumps on part of the top metal layer of the first wafer and on part of the top metal layer of the second wafer respectively, removing the top metal layer that is not directly beneath the bumps in the first wafer, and completely retaining the top metal layer in the second wafer, and packaging the first wafer to a first die and packaging the second wafer to a second die, wherein the second die is used as a test structure, and the electrical performance of the second die is used as a reference for electrical performance of the first die.

Abstract: The application discloses a method for manufacturing an electrical performance test structure of packaged chip, and a method for testing electrical performance of packaged chip, including: providing a first wafer and a second wafer, forming a top metal layer on the first wafer and the second wafer respectively, forming bumps on part of the top metal layer of the first wafer and on part of the top metal layer of the second wafer respectively, removing the top metal layer that is not directly beneath the bumps in the first wafer, and completely retaining the top metal layer in the second wafer, and packaging the first wafer to a first die and packaging the second wafer to a second die, wherein the second die is used as a test structure, and the electrical performance of the second die is used as a reference for electrical performance of the first die.

Abstract: A package substrate and a manufacturing method thereof, the method including: forming a package substrate by a first dielectric layer formed by weaving at least fiberglass of a first width and a second dielectric layer formed by weaving at least fiberglass of a second width. The second width is different from the first width, and the weaving direction of the fiberglass in the first dielectric layer is 90° relative to the weaving direction of the fiberglass in the second dielectric layer.

Abstract: The present application disclosed a conducting layer-dielectric layer-conducting layer (CDC) laminate structure and test method for detecting defects of an inter-metal dielectric layer. The laminate structure comprises: a dielectric layer formed on a substrate; a first conducting layer formed at a first side of the dielectric layer, wherein the first conducting layer includes a first metal region and at least one first opening in the first metal region; and a second conducting layer formed at a second side of the dielectric layer opposite to the first conducting layer such that the second conducting layer is separated from the first conducting layer by the dielectric layer, wherein the second conducting layer includes a second metal region and a plurality of second openings in the second metal region.

Abstract: The present application disclosed a conducting layer-dielectric layer-conducting layer (CDC) laminate structure and test method for detecting defects of an inter-metal dielectric layer. The laminate structure comprises: a dielectric layer formed on a substrate; a first conducting layer formed at a first side of the dielectric layer, wherein the first conducting layer includes a first metal region and at least one first opening in the first metal region; and a second conducting layer formed at a second side of the dielectric layer opposite to the first conducting layer such that the second conducting layer is separated from the first conducting layer by the dielectric layer, wherein the second conducting layer includes a second metal region and a plurality of second openings in the second metal region.