Abstract: An input device including: a first in-phase touch sensing block including: an analog mixer configured to mix a resulting signal associated with a capacitive sensor electrode with a local oscillator (LO) signal; an analog to digital converter (ADC) configured to convert an output of the analog mixer into a digital signal; and a first decimation filter configured to determine an in-phase component of an interference at a frequency of the LO signal based, at least in part, on the digital signal; and a first quadrature interference detection block including: a second decimation filter configured to determine a quadrature component of the interference at the frequency.

Abstract: An input device including: a first in-phase touch sensing block including: an analog mixer configured to mix a resulting signal associated with a capacitive sensor electrode with a local oscillator (LO) signal; an analog to digital converter (ADC) configured to convert an output of the analog mixer into a digital signal; and a first decimation filter configured to determine an in-phase component of an interference at a frequency of the LO signal based, at least in part, on the digital signal; and a first quadrature interference detection block including: a second decimation filter configured to determine a quadrature component of the interference at the frequency.

Abstract: An example circuit includes: a filter configured to process a digital signal through at least one stage; and a coefficient generator circuit configured to generate coefficients for the at least one stage of the filter. The coefficient generator circuit includes: a lookup-table (LUT) configured to output a differential sequence; an up-sampling holder circuit configured to up-sample and hold the differential sequence to generate an up-sampled differential sequence; and an accumulator configured to integrate the up-sampled differential sequence to generate the coefficients.

Abstract: An example circuit includes: a filter configured to process a digital signal through at least one stage; and a coefficient generator circuit configured to generate coefficients for the at least one stage of the filter. The coefficient generator circuit includes: a lookup-table (LUT) configured to output a differential sequence; an up-sampling holder circuit configured to up-sample and hold the differential sequence to generate an up-sampled differential sequence; and an accumulator configured to integrate the up-sampled differential sequence to generate the coefficients.

Abstract: An example circuit includes: a plurality of analog-to-digital converters (ADCs) receiving a respective plurality of analog signals and outputting a respective plurality of digital signals; a coefficient generator circuit outputting a coefficient signal; and a plurality of decimation filters each including a first input that receives a respective one of the plurality of digital signals and a second input that receives the coefficient signal, each of the plurality of decimation filters including a finite impulse response (FIR) filter having a multiplier and a single accumulator.

Abstract: Disclosed herein are methods, structures, and devices that provide multi-range frequency domain compensation of chromatic dispersion within optical transmission systems that offer significant operational power savings. More specifically, a method of operating frequency domain filtering structures and circuits including FFT, frequency-domain filter multiplication and iFFT functions at a lower duty cycle for shorter overlap such that significant power savings is realized.

Abstract: Disclosed herein are methods, structures, and devices that provide multi-range frequency domain compensation of chromatic dispersion within optical transmission systems that offer significant operational power savings. More specifically, a method of operating frequency domain filtering structures and circuits including FFT, frequency-domain filter multiplication and iFFT functions at a lower duty cycle for shorter overlap such that significant power savings is realized.

Abstract: The present invention provides a DC offset correction system for a wireless communication device that removes a DC offset from a baseband receive signal during “training time” when the baseband receive signal should ideally have no DC content. In general, the DC offset correction system includes multiple configurable feedback loops that operate to remove or cancel the DC offset from the baseband receive signal. One or more of the multiple configurable feedback loops is activated for a period of time during operation when it is known that the received signal should ideally contain no DC content. This training time varies depending on the particular communication standard being used by the wireless communication device. For example, the training time may be during reception of the preamble and header of an IEEE 802.11 packet.

Abstract: The present invention provides a method and apparatus for estimating a multipath channel with sub-chip resolution. In general, secondary signals are characterized based on correlating a received signal including multipath signals, which include a main and the secondary signals, with a pseudo-random noise code. An inverse filter operates to increase a temporal resolution of results of the correlation of the received signal and the pseudo-random noise code, thereby allowing secondary multipath signals occurring within the same chip interval as another multipath signal to be detected and estimated correctly.

Abstract: The equalizer of the present invention operates on input multipath signal samples, preferably at chip or sub-chip resolution, to remove or substantially cancel the effects of one or more secondary signals from the main path signal. Using predetermined path information for one or more of the secondary path signals, including magnitude, phase, and time offset relative to the main path signal, the equalizer compensates input multipath signal samples by subtracting estimated secondary signal values from the input samples. For each input sample, the equalizer forms a sliced sample, where the sliced sample represents a nominal phase value defined by the modulation scheme used in the original chip or symbol transmission that is closest in value to the actual phase of the input sample. These sliced samples are held in a running buffer and used, in combination with the predetermined path information and scaling logic, to form the estimated secondary signal values for compensating the input samples.

Abstract: An equalizer operates on chip or sub-chip resolution input samples of a received spread-spectrum multipath signal to remove interference from one or more secondary propagation path signals within the multipath signal. The equalizer may be configured for cancellation of secondary signals arriving before and after a main propagation path signal. The length of sample delay buffers and the input sample rate determine the maximum secondary signal delay accommodated by the equalizer. The equalizer makes a hard-decision about the phase value of each input sample and buffers these hard-decision values for use in secondary signal cancellation. The hard-decision values are used to rotate the phase of corresponding path coefficients. These adjusted values are fed back for subtraction from input samples for post-cursor cancellation, and fed forward for subtraction from delayed input samples for pre-cursor cancellation.

Abstract: The present invention provides a method and apparatus for estimating a multipath channel with sub-chip resolution. In general, secondary signals are characterized based on correlating a received signal including multipath signals, which include a main and the secondary signals, with a pseudo-random noise code. An inverse filter operates to increase a temporal resolution of results of the correlation of the received signal and the pseudo-random noise code, thereby allowing secondary multipath signals occurring within the same chip interval as another multipath signal to be detected and estimated correctly.

Abstract: An equalizer operates on chip or sub-chip resolution input samples of a received spread-spectrum multipath signal to remove interference from one or more secondary propagation path signals within the multipath signal. The equalizer may be configured for cancellation of secondary signals arriving before and after a main propagation path signal. The length of sample delay buffers and the input sample rate determine the maximum secondary signal delay accommodated by the equalizer. The equalizer makes a hard-decision about the phase value of each input sample and buffers these hard-decision values for use in secondary signal cancellation. The hard-decision values are used to rotate the phase of corresponding path coefficients. These adjusted values are fed back for subtraction from input samples for post-cursor cancellation, and fed forward for subtraction from delayed input samples for pre-cursor cancellation.

Abstract: An equalizer operates on chip or sub-chip resolution input samples of a received spread-spectrum multipath signal to remove interference from one or more secondary propagation path signals within the multipath signal. The equalizer may be configured for cancellation of secondary signals arriving before and after a main propagation path signal, referred to as pre- and post-cursor signals, respectively. An associated communications system provides the equalizer with a path coefficient and delay value for each secondary path signal for which cancellation is desired. With its unique architecture, the equalizer cancels secondary signals displaced in time by amounts as small as the input sample time resolution or by amounts exceeding multiple chips, or even multiple symbols. The length of sample delay buffers within the equalizer, in combination with the input sample rate, determines the maximum secondary signal delay accommodated by the equalizer.

Abstract: A training method provides an advantageous technique for estimating secondary propagation path parameters based on learning propagation path characteristics for a selected number of secondary propagation path signals. In a multipath environment, a received radio signal comprises multiple received signals, each received through a different signal propagation path. The strongest multipath signal is deemed the main path signal, while the remaining multipath signals are termed secondary path signals. In some types of direct-sequence, spread spectrum communications systems, significant secondary signals must be canceled from the received multipath signal to achieve desired receiver performance, while in other types of systems, such secondary signals may be used to enhance the signal-to-noise ratio of the received signal. In either case, the various multipath signals must be accurately characterized.

Abstract: The equalizer of the present invention operates on input multipath signal samples, preferably at chip or sub-chip resolution, to remove or substantially cancel the effects of one or more secondary signals from the main path signal. Using predetermined path information for one or more of the secondary path signals, including magnitude, phase, and time offset relative to the main path signal, the equalizer compensates input multipath signal samples by subtracting estimated secondary signal values from the input samples. For each input sample, the equalizer forms a sliced sample, where the sliced sample represents a nominal phase value defined by the modulation scheme used in the original chip or symbol transmission that is closest in value to the actual phase of the input sample. These sliced samples are held in a running buffer and used, in combination with the predetermined path information and scaling logic, to form the estimated secondary signal values for compensating the input samples.

Abstract: The receiver receives a complex spread spectrum signal modulated using complementary code keying. The received signal is down converted and cross correlated with code words using a Fast Walsh Transform. The peak magnitudes resulting from the Fast Walsh Transform are selected for a period before, during, and after an expected symbol boundary. The relative magnitudes of the early, on-time and late measurements are compared to determine which output has the largest magnitude. If the on-time measurement is the largest, symbol tracking continues without a timing adjustment. If the early measurement has the greatest magnitude, then the tracking timing is adjusted one period downward to shorten the period expected before the next symbol boundary. If the late measurement has the largest magnitude, then the tracking timing is increased by one sample period to increase the period expected before the next symbol boundary. This process repeats itself to provide accurate symbol tracking.

Abstract: The present invention groups a set of N, nearly orthogonal, CCK code words into M subgroups, with each subgroup consisting of N/M orthogonal code words. For the 64-ary CCK communication standard for wireless local area networks (WLAN), N is 64 and M is preferably 8. Based on the orthogonal subgrouping, most significant bit (MSB) comparitors, instead of full-scale comparitors, are used to compare cross-correlations for each subgroup. In the subgroup containing the desired maximum correlation, all other cross-correlations, except the maximum, are zero in an ideal case, or very close to zero in a noisy environment due to the selected orthogonality. The maximum correlation value can be distinguished by looking at only the most significant bit or bits among all the cross-correlations. In the subgroups that do not contain the global, maximum correlation value, it does not matter which cross-correlation value is picked.

Abstract: Carrier recovery control circuitry incorporates a dual-phase accumulator architecture to facilitate carrier recovery in spread spectrum communications. The associated receiver is configured to downconvert and despread the spread spectrum signal to a baseband signal. Demodulation circuitry operating on the baseband signals provides an error signal representing the difference between the sampled signal and the ideal symbol. This error signal, through a loop filter, is to provided to a first phase accumulator running at the symbol rate. The first phase accumulator accumulates a first phase correction adjustment for each symbol duration. A second phase accumulator running at the sampling rate is set by the output of the first phase accumulator to cause the second phase accumulator to accumulate an additional phase correction adjustment that is dependent upon the first phase correction adjustment and the sample rate.

Abstract: A training circuit includes resources for processing magnitude and phase information received in a main propagation path signal with magnitude and phase information concurrently received in a secondary propagation path signal to determine values for magnitude, phase, and time offset of the secondary propagation path signal relative to the main propagation path signal. Differential decoding circuitry within the training circuit provides a correlation circuit, also in the training circuit, with differentially decoded sequences of symbol phase values derived from concurrent main and secondary signal propagation path symbol phase value sequences provided to the training circuit by an associated communications receiver.