Abstract: An embodiment of the invention provides an isolation cell for isolating a second power domain from a first power domain. The isolation cell includes an input terminal capable of receiving a first signal of the first power domain, an output terminal capable of outputting an output signal with a predetermined logic state to the second power domain, a first power terminal and a second power terminal. The first power terminal is capable of receiving a voltage from a power source, the power source is different from a first power source of the first power domain, and the isolation cell is powered by the voltage.

Abstract: An embodiment of the invention provides an isolation cell for isolating a second power domain from a first power domain. The isolation cell includes an input terminal capable of receiving a first signal of the first power domain, an output terminal capable of outputting an output signal with a predetermined logic state to the second power domain, a first power terminal and a second power terminal The first power terminal is capable of receiving a voltage from a power source, the power source is different from a first power source of the first power domain, and the isolation cell is powered by the voltage.

Abstract: A global positioning system (GPS) device including an antenna and a baseband unit is disclosed. The antenna receives a wireless signal group. The baseband unit processes the wireless signal group to generate a position signal. The position signal is updated every time interval. The duration of the time interval is changed dynamically.

Abstract: A global positioning system (GPS) device including an antenna and a baseband unit is disclosed. The antenna receives a wireless signal group. The baseband unit processes the wireless signal group to generate a position signal. The position signal is updated every time interval. The duration of the time interval is changed dynamically.

Abstract: A clock architecture including a clock source, a multi-phase clock signal generator, a control bus, a number of clock signal lines, and at least one circuit block. The clock source generates a global clock signal, which is then transferred to the multi-phase clock signal generator connected to the clock source. Upon receipt of global clock signal, the multi-phase clock signal generator, which is connected to a control bus, generates clock signals of different phases according to the signals from the control bus. Each of the clock signal branches transfers one of the clock signals of different phases, wherein each of the clock signal branches is individually connected to the circuit block through an electrical switch. Only one switch is at an on state at one time, so that the clock signal of a corresponding phase is transferred to the circuit block. The driving forces applied on the clock buffer connected to the clock source and the clock buffers on the branches are adjustable for reducing clock skew.