Patents by Inventor Peng Fei Gou
Peng Fei Gou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210397476Abstract: A method comprises receiving a workload for a computer system; sweeping at least one parameter of the computer system while executing the workload; monitoring one or more characteristics of the computer system while sweeping the at least one parameter, the one or more characteristics including total power consumption of the computer system; generating a power profile for the workload that indicates a respective selected value for the at least one parameter based on analysis of the monitored total power consumption of the computer system while sweeping the at least one parameter; and executing the workload based on the respective selected value of the at least one parameter.Type: ApplicationFiled: June 18, 2020Publication date: December 23, 2021Inventors: Yang Liu, Yue Xu, Peng Fei Gou, Meng Li, Xing Zhao
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Patent number: 11120185Abstract: The computer processor identifies a first shared set of input ports that are common to a first hardware model and a second hardware model and a second shared set of input ports that are common to a first reference model and a second reference model. The computer processor selects logic of the first hardware model and logic of the second hardware model that are each traceable to the first shared set of input ports and selects logic of the first reference model and logic of the second reference model that are each traceable to the second shared set of input ports. The computer processor determines that the logic of the second hardware model and the logic of the second reference model have verified logic by determining that the logic of the first hardware model is equivalent to the logic of the second hardware model and the logic of the first reference model is equivalent to the logic of the second reference model.Type: GrantFiled: November 29, 2018Date of Patent: September 14, 2021Assignee: International Business Machines CorporationInventors: Yan Heng Lu, Chen Qian, Zhen Peng Zuo, Heng Liu, Peng Fei Gou, Yang Fan Liu
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Patent number: 11048630Abstract: A symmetrical multi-processing (SMP) node, a distributed SMP (DSMP) system comprising a plurality of SMP nodes, and a method implemented in the SMP node are disclosed. The SMP node comprises: a plurality of processors, a memory coupled to the plurality of processors, and a memory coherent proxy coupled to the plurality of processors through a coherent accelerator interface. The memory coherent proxy is configured to manage statuses of cache lines in the memory.Type: GrantFiled: November 27, 2018Date of Patent: June 29, 2021Assignee: International Business Machines CorporationInventors: Zhen Peng Zuo, Peng Fei Gou, Yang Fan Liu, Yang Liu, Hua Xin Yao
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Patent number: 10769331Abstract: An apparatus for verification includes a processing module, a data collection module, an engine selection module and an engine execution module. The processing module processes a netlist using a plurality of engines. The netlist includes components and nodes of an integrated circuit design. Each engine includes an algorithm for verification of the integrated circuit design. The data collection module stores, for each engine, execution results for the engine for a plurality of netlists, the results stored in a history buffer. The engine selection module, for a current netlist, calculates using execution results in the history buffer which engine of the plurality of engines has a highest predicted performance and selects the engine with the highest predicted performance. The engine execution module executes the current netlist using the selected engine to produce execution results, reports the execution results and stores the execution results in the history buffer.Type: GrantFiled: July 12, 2018Date of Patent: September 8, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peng Fei Gou, Heng Liu, Yang Fan Liu, Yan Heng Lu, Chen Qian, Zhen Peng Zuo
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Patent number: 10699044Abstract: An apparatus for model splitting includes an extraction module that extracts netlist parameters from a static netlist. The netlist parameters include node parameters of each node of the static netlist. The node parameters include node connection information and execution cycle information. The nodes of the static netlist include nodes of an integrated circuit design from an input to an output. A split node module analyzes, using the netlist parameters, each node in a cycle and determines if each node is a potential split node, which is a node with a projected sub-proof execution time less than a time limit. A split chain module determines if a split chain exists. The split chain includes a connection between potential split nodes from the input to the output at each execution cycle. A reporting module reports nodes of a split chain in response to determining that a split chain exists.Type: GrantFiled: July 13, 2018Date of Patent: June 30, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chen Qian, Heng Liu, Peng Fei Gou, Yang Fan Liu, Yan Heng Lu, Zhen Peng Zuo
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Publication number: 20200175128Abstract: The computer processor identifies a first shared set of input ports that are common to a first hardware model and a second hardware model and a second shared set of input ports that are common to a first reference model and a second reference model. The computer processor selects logic of the first hardware model and logic of the second hardware modelt that are each traceable to the first shared set of input ports and selects logic of the first reference model and logic of the second reference model that are each traceable to the second shared set of input ports. The computer processor determines that the logic of the second hardware model and the logic of the second reference model have verified logic by determining that the logic of the first hardware model is equivalent to the logic of the second hardware model and the logic of the first reference model is equivalent to the logic of the second reference model.Type: ApplicationFiled: November 29, 2018Publication date: June 4, 2020Inventors: Yan Heng LU, Chen QIAN, Zhen Peng ZUO, Heng LIU, Peng Fei GOU, Yang Fan LIU
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Publication number: 20200167283Abstract: A symmetrical multi-processing (SMP) node, a distributed SMP (DSMP) system comprising a plurality of SMP nodes, and a method implemented in the SMP node are disclosed. The SMP node comprises: a plurality of processors, a memory coupled to the plurality of processors, and a memory coherent proxy coupled to the plurality of processors through a coherent accelerator interface. The memory coherent proxy is configured to manage statuses of cache lines in the memory.Type: ApplicationFiled: November 27, 2018Publication date: May 28, 2020Inventors: Zhen Peng Zuo, Peng Fei Gou, Yang Fan Liu, Yang Liu, Hua Xin Yao
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Patent number: 10614192Abstract: A method and apparatus for ranking combinations of mutants, test cases and random seeds in mutation testing, comprising obtaining, based on a signal of a test case target, logic gates related to the signal of the test case target and mutants on the related logic gates, for a compiled integrated circuit under test; calculating distances between the mutants and the signal of the test case target; performing a circuit simulation on the compiled integrated circuit under test to obtain activation cycle numbers corresponding to combinations of the mutants, test cases and random seeds; obtaining activation cycle number variances corresponding to combinations of the mutants and the test cases; and ranking the combinations of the mutants, the test cases and the random seeds based on the distances, the activation cycle numbers and the activation cycle number variances. The invention can reduce the probability that the mutation simulation selects equivalent mutants.Type: GrantFiled: January 18, 2018Date of Patent: April 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peng Fei Gou, Bodo Hoppe, Yang Li, Dan Liu, Yang Liu
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Publication number: 20200019654Abstract: An apparatus for verification includes a processing module, a data collection module, an engine selection module and an engine execution module. The processing module processes a netlist using a plurality of engines. The netlist includes components and nodes of an integrated circuit design. Each engine includes an algorithm for verification of the integrated circuit design. The data collection module stores, for each engine, execution results for the engine for a plurality of netlists, the results stored in a history buffer. The engine selection module, for a current netlist, calculates using execution results in the history buffer which engine of the plurality of engines has a highest predicted performance and selects the engine with the highest predicted performance. The engine execution module executes the current netlist using the selected engine to produce execution results, reports the execution results and stores the execution results in the history buffer.Type: ApplicationFiled: July 12, 2018Publication date: January 16, 2020Inventors: PENG FEI GOU, HENG LIU, YANG FAN LIU, YAN HENG LU, CHEN QIAN, ZHEN PENG ZUO
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Publication number: 20200019652Abstract: An apparatus for model splitting includes an extraction module that extracts netlist parameters from a static netlist. The netlist parameters include node parameters of each node of the static netlist. The node parameters include node connection information and execution cycle information. The nodes of the static netlist include nodes of an integrated circuit design from an input to an output. A split node module analyzes, using the netlist parameters, each node in a cycle and determines if each node is a potential split node, which is a node with a projected sub-proof execution time less than a time limit. A split chain module determines if a split chain exists. The split chain includes a connection between potential split nodes from the input to the output at each execution cycle. A reporting module reports nodes of a split chain in response to determining that a split chain exists.Type: ApplicationFiled: July 13, 2018Publication date: January 16, 2020Inventors: CHEN QIAN, HENG LIU, PENG FEI GOU, YANG FAN LIU, YAN HENG LU, ZHEN PENG ZUO
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Publication number: 20180144090Abstract: A method and apparatus for ranking combinations of mutants, test cases and random seeds in mutation testing, comprising obtaining, based on a signal of a test case target, logic gates related to the signal of the test case target and mutants on the related logic gates, for a compiled integrated circuit under test; calculating distances between the mutants and the signal of the test case target; performing a circuit simulation on the compiled integrated circuit under test to obtain activation cycle numbers corresponding to combinations of the mutants, test cases and random seeds; obtaining activation cycle number variances corresponding to combinations of the mutants and the test cases; and ranking the combinations of the mutants, the test cases and the random seeds based on the distances, the activation cycle numbers and the activation cycle number variances. The invention can reduce the probability that the mutation simulation selects equivalent mutants.Type: ApplicationFiled: January 18, 2018Publication date: May 24, 2018Inventors: Peng Fei GOU, Bodo HOPPE, Yang LI, Dan LIU, Yang LIU
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Patent number: 9965580Abstract: A method and apparatus for ranking combinations of mutants, test cases and random seeds in mutation testing, comprising obtaining, based on a signal of a test case target, logic gates related to the signal of the test case target and mutants on the related logic gates, for a compiled integrated circuit under test; calculating distances between the mutants and the signal of the test case target; performing a circuit simulation on the compiled integrated circuit under test to obtain activation cycle numbers corresponding to combinations of the mutants, test cases and random seeds; obtaining activation cycle number variances corresponding to combinations of the mutants and the test cases; and ranking the combinations of the mutants, the test cases and the random seeds based on the distances, the activation cycle numbers and the activation cycle number variances. The invention can reduce the probability that the mutation simulation selects equivalent mutants.Type: GrantFiled: June 24, 2015Date of Patent: May 8, 2018Assignee: NTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peng Fei Gou, Bodo Hoppe, Yang Li, Dan Liu, Yang Liu
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Patent number: 9928884Abstract: An integrated circuit (IC) can dynamically manage memory communication paths between multiple processors and multiple memory modules. The IC can include upstream logic that performs data conversion and provides memory communication paths between each processor and a corresponding upstream port. An interconnect layer in the IC can be electrically coupled to the upstream ports to multiple downstream ports. An interconnect management processor electrically coupled to the interconnect layer can respond to received commands by executing an allocation program stored in a read-only memory (ROM) that dynamically establishes and terminates memory communication paths between the upstream ports and the downstream ports. A memory interface layer in the IC can be electrically coupled to the downstream ports and to the memory modules, and can provide, through corresponding memory physical interfaces, memory communication paths between the multiple downstream ports and corresponding memory modules.Type: GrantFiled: May 1, 2017Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: Peng Fei Gou, Jin Song Jiang, Yufei Li, Heng Liu, ZeQiang Xiao
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Patent number: 9443044Abstract: Determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. A netlist is generated from the hardware design language description. A list of hardware design outputs is generated, and logical paths in the netlist are generated based on the list of hardware design outputs. Furthermore, a modified netlist involving logical paths is generated by determining whether a gate is selected as an insertion point, and selecting a fault type, which is part of the efficiency vector for the selected gate in the netlist and inserting a mutant. Additionally, a fault simulation is performed and the quality parameter for the verification environment is determined from the fault simulation and the simulation result data.Type: GrantFiled: October 20, 2014Date of Patent: September 13, 2016Assignee: International Business Machines CorporationInventors: Peng Fei Gou, Bodo Hoppe, Dan Liu, Yong Feng Pan
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Publication number: 20160063158Abstract: The present invention discloses a method and device for simulating a circuit design. The method includes identifying at least one Sequential-cell-To-Sequential-cell (S2S) block in the circuit design, wherein the S2S block includes at least one input sequential cell, at least one output sequential cell, and an intermediate portion between the input sequential cell and the output sequential cell, wherein the intermediate portion includes at least one combinational cell; determining logic characteristics and timing characteristics of the intermediate portion; and replacing the intermediate portion with a functional module having the logic characteristics and the timing characteristics to generate a simplified circuit design to be used in simulation. With the technical solution according to embodiments of the invention, time needed in simulation is shortened.Type: ApplicationFiled: June 24, 2015Publication date: March 3, 2016Inventors: Peng Fei Gou, De Xian Li, Yu Fei Li, Yang Liu, Peng Ou
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Publication number: 20150379187Abstract: A method and apparatus for ranking combinations of mutants, test cases and random seeds in mutation testing, comprising obtaining, based on a signal of a test case target, logic gates related to the signal of the test case target and mutants on the related logic gates, for a compiled integrated circuit under test; calculating distances between the mutants and the signal of the test case target; performing a circuit simulation on the compiled integrated circuit under test to obtain activation cycle numbers corresponding to combinations of the mutants, test cases and random seeds; obtaining activation cycle number variances corresponding to combinations of the mutants and the test cases; and ranking the combinations of the mutants, the test cases and the random seeds based on the distances, the activation cycle numbers and the activation cycle number variances. The invention can reduce the probability that the mutation simulation selects equivalent mutants.Type: ApplicationFiled: June 24, 2015Publication date: December 31, 2015Inventors: Peng Fei GOU, Bodo HOPPE, Yang LI, Dan LIU, Yang LIU
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Publication number: 20150121323Abstract: Determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. A netlist is generated from the hardware design language description. A list of hardware design outputs is generated, and logical paths in the netlist are generated based on the list of hardware design outputs. Furthermore, a modified netlist involving logical paths is generated by determining whether a gate is selected as an insertion point, and selecting a fault type, which is part of the efficiency vector for the selected gate in the netlist and inserting a mutant. Additionally, a fault simulation is performed and the quality parameter for the verification environment is determined from the fault simulation and the simulation result data.Type: ApplicationFiled: October 20, 2014Publication date: April 30, 2015Inventors: Peng Fei Gou, Bodo Hoppe, Dan Liu, Yong Feng Pan