Abstract: A device is provided, including a dielectric layer, a plurality of first conductive segments within the dielectric layer and spaced apart from each other by respective first spacings, and a plurality of second conductive segments within the dielectric layer and spaced apart from each other by respective second spacings. The plurality of second conductive segments may be over and spaced apart from the plurality of first conductive segments by the dielectric layer. A respective one of the first conductive segments may at least partially extend across a corresponding one of the second spacings, and a respective one of the second conductive segments may at least partially extend across a corresponding one of the first spacings.

Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a substrate including a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads. The electronic assembly may include a first device including a first footprint coupled to the substrate at a first surface. The electronic assembly may include a frame arranged between the first device and the substrate, the frame including a dielectric material, the frame further including a main frame extending around the first device, and further including a plurality of sub-frames encircling the plurality of first contact pads and the plurality of second contact pads on the substrate, wherein the frame may further include a conductive layer extending at least partially across the main frame.

Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a package substrate with a top substrate surface and an interposer coupled to the package substrate at the top substrate surface. The interposer may include a plurality of through interposer vias and an opening extending through the interposer. A power module may be arranged in the opening in the interposer and coupled to the package substrate at the top substrate surface. The power module may include a plurality of interconnects including a first interconnect coupled to a first voltage and a second interconnect coupled to a second voltage.

Abstract: A device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. The first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. The second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.

Abstract: Semiconductor packages, and methods for making the semiconductor packages, having an interposer structure with one or more interposer and an extension platform, which has an opening for placing the interposer, and the space between the interposer and the extension platform is filled with a polymeric material to form a unitary interposer-extension platform composite structure. A stacked structure may be formed by at least a first semiconductor chip coupled to the interposer and at least a second semiconductor chip coupled to the extension platform, and at least one bridge extending over the space that electrically couples the extension platform and the interposer. The extension platform may include a recess step section that may accommodate a plurality of passive devices to reduced power delivery inductance loop for the high-density 2.5D and 3D stacked packaging applications.

Abstract: The present disclosure is directed to semiconductor packages incorporating composite or hybrid bridges that include first and second interconnect bridges positioned on a substrate and a power corridor with a plurality of vertical channels positioned on the substrate between the first and second interconnect bridges, wherein the power corridor integrally joins the first interconnect bridge to the second interconnect bridge.

Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a substrate and a first die with first and second opposing surfaces. The first die may be coupled to the substrate at the first surface. At least one first trench may extend partially through the first die from the second surface. A stiffener may be attached to the substrate. The stiffener may have a cavity that accommodates the first die, in which the second surface of the first die faces the stiffener. A thermally conductive layer may be positioned between the stiffener and the first die. The conductive layer at least partially fills the at least one first trench.

Abstract: A disposable absorbent article such as a diaper, pant diaper, a sanitary pant or incontinence garment, intended to be worn around the waist of a wearer is provided. The absorbent article has a chassis having a front portion, a back portion and a crotch portion therebetween. The absorbent article optionally has one or more fastening tabs attached to the back or front portion of the chassis. The absorbent article has an absorbent core secured to the chassis in at least the crotch portion. The absorbent article is provided with a QR-code on a garment facing-side thereof and on a carrier material in or on at least one of the front portion, back portion and/or on the one or more fastening tabs. The carrier material has a Gurley stiffness of 8 mgf or more.

Abstract: One example includes a test system that includes a printed circuit board and a switching interposer board. The switching interposer board is comprised of a probe point, a first bus, a second bus, and a set of switches. Each switch includes a first terminal, a second terminal, and a third terminal, the first terminal being coupled to a respective pin of an integrated circuit device, the second terminal being coupled to the first bus, and the third terminal being coupled to the second bus. Each of the set of switches have a first state that selectively couples a pair of the pins of the integrated circuit device to each other through the first bus during a short test, and a second state that selectively couples at least one of the pins of the integrated circuit device to the probe point through the second bus during a voltage level spike test.

Abstract: One example includes a test system that includes a printed circuit board and a switching interposer board. The switching interposer board is comprised of a probe point, a first bus, a second bus, and a set of switches. Each switch includes a first terminal, a second terminal, and a third terminal, the first terminal being coupled to a respective pin of an integrated circuit device, the second terminal being coupled to the first bus, and the third terminal being coupled to the second bus. Each of the set of switches have a first state that selectively couples a pair of the pins of the integrated circuit device to each other through the first bus during a short test, and a second state that selectively couples at least one of the pins of the integrated circuit device to the probe point through the second bus during a voltage level spike test.

Abstract: An electronic package that has an array of pins may be tested for shorts and continuity in a parallel manner. The array of pins are allocated to four or more groups of pins such that each pin in each group is not adjacent to a pin from its own group of pins. One of the groups of pins is tested for continuity while placing a reference voltage level on all of the pins in the other groups of pins. A separate current source is coupled to each pin and a resultant voltage is measured. A short between one of the pins in the first group and a pin in one of the other groups can be detected when the resultant voltage on one of the pins in the first group is approximately equal to the reference voltage. Group-wise testing is repeated until all groups have been tested.

Abstract: An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously connecting multiple output pins directly to ground in order to active a current limiter associated with each of the output pins. The pins are then connected to a resistive connection to ground via a set of resistors; the direct ground is then removed, such that the current limiter associated with each of the output pins remains activated. A voltage drop across each of the set of resistors is measured simultaneously. An output short circuit current fault is indicated when the voltage drop across any of the resistors exceeds a threshold value corresponding to a maximum output short circuit current value.

Abstract: An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously connecting multiple output pins directly to ground in order to active a current limiter associated with each of the output pins. The pins are then connected to a resistive connection to ground via a set of resistors; the direct ground is then removed, such that the current limiter associated with each of the output pins remains activated. A voltage drop across each of the set of resistors is measured simultaneously.

Abstract: An electronic package that has an array of pins may be tested for shorts and continuity in a parallel manner. The array of pins are allocated to four or more groups of pins such that each pin in each group is not adjacent to a pin from its own group of pins. One of the groups of pins is tested for continuity while placing a reference voltage level on all of the pins in the other groups of pins. A separate current source is coupled to each pin and a resultant voltage is measured. A short between one of the pins in the first group and a pin in one of the other groups can be detected when the resultant voltage on one of the pins in the first group is approximately equal to the reference voltage. Group-wise testing is repeated until all groups have been tested.

Abstract: A process for automated via doubling in a layout of a semiconductor device, comprising: selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers; selecting at least two metal layers of the at least one cell for via doubling; selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection comprises an existing via interconnecting a plurality of metal layers; and dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout.

Abstract: A process for automated via doubling in a layout of a semiconductor device, comprising: selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers; selecting at least two metal layers of the at least one cell for via doubling; selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection comprises an existing via interconnecting a plurality of metal layers; and dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout.

Abstract: A system is provided that facilitates locating long dangling metal routes in a semiconductor chip design. The system includes mechanisms for partitioning metal features of the chip design to discover dangling metal routes that could be potential violations. The system further comprises mechanisms for determining if the dangling metal routes of the chip design exceed a length limit that could result antenna violations, undesired noise in the circuit, circuitry breakdown or the like. The system enables excessively long dangling metal routes to be allowed as exceptional cases. Machine learning is provided to receive feedback to refine the exceptional cases and enable more efficient fault detection.

Abstract: A system is provided that facilitates locating long dangling metal routes in a semiconductor chip design. The system includes mechanisms for partitioning metal features of the chip design to discover dangling metal routes that could be potential violations. The system further comprises mechanisms for determining if the dangling metal routes of the chip design exceed a length limit that could result antenna violations, undesired noise in the circuit, circuitry breakdown or the like. The system enables excessively long dangling metal routes to be allowed as exceptional cases. Machine learning is provided to receive feedback to refine the exceptional cases and enable more efficient fault detection.

Abstract: A method and apparatus for automatic user authentication are described. The method includes receiving information at a device, the device including a credential container; storing the information at the credential container and performing cryptographic calculations on the received information and providing the encrypted information upon request.

Abstract: A method and system for protecting electronic files by applying a portable access control lock to each electronic file while allowing multi-user access to the protected electronic files across a distributed network is described. The portable access control lock is adapted for implementing a set of complex access control rules that include managing an audit trail for the corresponding protected electronic file.