Patents by Inventor Peng Siang Seet

Peng Siang Seet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9520920
    Abstract: Various embodiments of systems for transmitting and receiving a plurality of signals across an isolation material are disclosed. In one embodiment, a first signal may be modulated into a first modulated signal. The first modulated signal is then modulated into a second modulated signal in accordance to a second signal using amplitude modulation. In another embodiment, a first signal and a second signal are modulated into a modulated signal before being modulated further using amplitude modulation. The detection of the modulated signal may be performed using a frequency detector and an amplitude detection circuit that are arranged in parallel. At least some of the apparatuses, circuits, systems and methods disclosed herein may be implemented using conventional CMOS design and manufacturing techniques to provide, for example, at least one or more integrated circuits.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: December 13, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Gek Yong Ng, Peng Siang Seet, Qian Tao, Kwee Chong Chang
  • Publication number: 20160119029
    Abstract: Various embodiments of systems for transmitting and receiving a plurality of signals across an isolation material are disclosed. In one embodiment, a first signal may be modulated into a first modulated signal. The first modulated signal is then modulated into a second modulated signal in accordance to a second signal using amplitude modulation. In another embodiment, a first signal and a second signal are modulated into a modulated signal before being modulated further using amplitude modulation. The detection of the modulated signal may be performed using a frequency detector and an amplitude detection circuit that are arranged in parallel. At least some of the apparatuses, circuits, systems and methods disclosed herein may be implemented using conventional CMOS design and manufacturing techniques to provide, for example, at least one or more integrated circuits.
    Type: Application
    Filed: October 27, 2014
    Publication date: April 28, 2016
    Inventors: Gek Yong Ng, Peng Siang Seet, Qian Tao, Kwee Chong Chang
  • Patent number: 9191124
    Abstract: An opto-isolator with a correction circuit is disclosed. The correction circuit is configured to make adjustments for degradation of the light source of the opto-isolator. The correction circuit may comprise a photodetector for detecting degradation of the light source of the opto-isolator. When the light source degrades below a predetermined level, the correction circuit may be configured to make adjustments.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: November 17, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Gopinath Maasi, Thiam Siew Tay, Soo Kiang Ho, Peng Siang Seet
  • Patent number: 9065461
    Abstract: An isolation device having first and second semiconductor is disclosed. The first semiconductor die may be adapted to transmit a first signal to the second semiconductor die that is electrically isolated. The first semiconductor die may comprise input terminals, a bitstream encoding circuit, a self-synchronizing encoding circuit and a transmitter. The second semiconductor die may comprise a receiver, a self-synchronizing decoder, a bitstream decoding circuit and an optional digital filter. The bitstream encoding and decoding may enable a plurality of signals to be encoded and transmitted through an isolation material.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: June 23, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Chee Heng Wong, Hui Fung Sim, Peng Siang Seet
  • Patent number: 8983304
    Abstract: An opto-isolator with a compensation circuit is disclosed. The compensation circuit may be configured to compensate degradation of the light source of the opto-isolator. The compensation circuit may comprise a circuit for counting an extended use of the isolator. When the count value exceeds a predetermined count value, the compensation circuit may be configured to compensate the degradation of the light source by adjusting the driver of the light source. In another embodiment, an electrical control system having such opto-isolator is illustrated.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 17, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Thiam Siew Tay, Gopinath Massi, Soo Kiang Ho, Peng Siang Seet
  • Publication number: 20140119739
    Abstract: An opto-isolator with a correction circuit is disclosed. The correction circuit is configured to make adjustments for degradation of the light source of the opto-isolator. The correction circuit may comprise a photodetector for detecting degradation of the light source of the opto-isolator. When the light source degrades below a predetermined level, the correction circuit may be configured to make adjustments.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd
    Inventors: Gopinath Maasi, Thiam Siew Tay, Soo Kiang Ho, Peng Siang Seet
  • Publication number: 20140119740
    Abstract: An opto-isolator with a compensation circuit is disclosed. The compensation circuit may be configured to compensate degradation of the light source of the opto-isolator. The compensation circuit may comprise a circuit for counting an extended use of the isolator. When the count value exceeds a predetermined count value, the compensation circuit may be configured to compensate the degradation of the light source by adjusting the driver of the light source. In another embodiment, an electrical control system having such opto-isolator is illustrated.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Thiam Siew Tay, Gopinath Massi, Soo Kiang Ho, Peng Siang Seet
  • Patent number: 8629714
    Abstract: According to one embodiment, there is provided a method of reducing the amount of power consumed by a galvanic isolator. A transmitter transmits a wake-up signal to a receiver located across an isolation medium when the transmitter is ready or preparing to transmit data or power signals to a receiver, which is operably connected to a sensing circuit. The sensing circuit receives the wake-up signal through the isolation medium, which may be operably connected to and powered substantially continuously or intermittently by a first power source. In response to the sensing circuit receiving the wake-up signal, the receiver is powered up from a sleep mode to an operating mode. After a period of time tRDY has passed since the wake-up signal was transmitted, a signature pattern is transmitted from the transmitter to the sensing circuit through the isolation medium. Next, the sensing circuit or the receiver verifies the validity of the signature pattern.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: January 14, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Gek Yong Ng, Peng Siang Seet, Fun Kok Chow
  • Publication number: 20100329363
    Abstract: According to one embodiment, there is provided a method of reducing the amount of power consumed by a galvanic isolator. A transmitter transmits a wake-up signal to a receiver located across an isolation medium when the transmitter is ready or preparing to transmit data or power signals to a receiver, which is operably connected to a sensing circuit. The sensing circuit receives the wake-up signal through the isolation medium, which may be operably connected to and powered substantially continuously or intermittently by a first power source. In response to the sensing circuit receiving the wake-up signal, the receiver is powered up from a sleep mode to an operating mode. After a period of time tRDY has passed since the wake-up signal was transmitted, a signature pattern is transmitted from the transmitter to the sensing circuit through the isolation medium. Next, the sensing circuit or the receiver verifies the validity of the signature pattern.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Applicant: Avago Technologies ECBU (Singapore) Pte. Ltd.
    Inventors: Gek Yong Ng, Peng Siang Seet, Fun Kok Chow