Patents by Inventor Peng Suo
Peng Suo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170987Abstract: The present application provides a shared energy storage scheduling method and system based on energy frequency regulation and load demand. The method includes: establishing an objective function of a shared energy storage system participating in cooperative scheduling of energy frequency regulation and load demand; inputting relevant parameters of a grid side, a user side and the shared energy storage system into the objective function; solving the objective function according to an objective function constraint condition and a switching cost of a load importance degree and in combination with a mixed integer linear programming algorithm, to obtain a shared energy storage configuration scheme; configuring the shared energy storage system according to the shared energy storage configuration scheme, and controlling the shared energy storage system to participate in energy cooperative scheduling of the grid side and the user side according to a hierarchical control strategy of the shared energy storage system.Type: ApplicationFiled: December 20, 2023Publication date: May 23, 2024Inventors: Kelan SUO, Peng LI, Lin CHENG, Ziyi ZHANG, Yongshui GUO, Shujun LIU, Xuyan ZHOU
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Publication number: 20240110284Abstract: A method of processing a substrate is disclosed which includes depositing a layer in a processing chamber on a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a hardness of a portion of the layer deposited on the sidewall region is lower than a hardness of a portion of the layer deposited on the field region, and lower than a hardness of a portion of the layer deposited on the fill region.Type: ApplicationFiled: September 26, 2023Publication date: April 4, 2024Inventors: Lulu XIONG, Kevin Hsiao, Chris LIU, Chieh-Wen LO, Sean M. SEUTTER, Deenesh PADHI, Prayudi LIANTO, Peng SUO, Guan Huei SEE, Zongbin WANG, Shengwei ZENG, Balamurugan RAMASAMY
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Publication number: 20240087958Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Peng SUO, Ying W. WANG, Guan Huei SEE, Chang Bum YONG, Arvind SUNDARRAJAN
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Patent number: 11854886Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.Type: GrantFiled: June 23, 2022Date of Patent: December 26, 2023Assignee: Applied Materials, Inc.Inventors: Peng Suo, Ying W. Wang, Guan Huei See, Chang Bum Yong, Arvind Sundarrajan
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Patent number: 11791094Abstract: A method of forming a magnetic core on a substrate having a stacked inductor coil includes etching a plurality of polymer layers to form at least one feature through the plurality of polymer layers, wherein the at least one feature is disposed within a central region of a stacked inductor coil formed on the substrate; and depositing a magnetic material within the at least one feature.Type: GrantFiled: April 11, 2021Date of Patent: October 17, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Peng Suo, Yu Gu, Guan Huei See, Arvind Sundarrajan
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Publication number: 20220328354Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.Type: ApplicationFiled: June 23, 2022Publication date: October 13, 2022Inventors: Peng SUO, Ying W. WANG, Guan Huei SEE, Chang Bum YONG, Arvind SUNDARRAJAN
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Patent number: 11404318Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.Type: GrantFiled: November 20, 2020Date of Patent: August 2, 2022Assignee: Applied Materials, Inc.Inventors: Peng Suo, Ying W. Wang, Guan Huei See, Chang Bum Yong, Arvind Sundarrajan
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Patent number: 11373803Abstract: A method of forming a magnetic core on a substrate having a stacked inductor coil includes etching a plurality of polymer layers to form at least one feature through the plurality of polymer layers, wherein the at least one feature is disposed within a central region of a stacked inductor coil formed on the substrate; and depositing a magnetic material within the at least one feature.Type: GrantFiled: August 7, 2018Date of Patent: June 28, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Peng Suo, Yu Gu, Guan Huei See, Arvind Sundarrajan
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Publication number: 20220165621Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.Type: ApplicationFiled: November 20, 2020Publication date: May 26, 2022Inventors: Peng SUO, Ying W. WANG, Guan Huei SEE, Chang Bum YONG, Arvind SUNDARRAJAN
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Publication number: 20210233707Abstract: A method of forming a magnetic core on a substrate having a stacked inductor coil includes etching a plurality of polymer layers to form at least one feature through the plurality of polymer layers, wherein the at least one feature is disposed within a central region of a stacked inductor coil formed on the substrate; and depositing a magnetic material within the at least one feature.Type: ApplicationFiled: April 11, 2021Publication date: July 29, 2021Inventors: Peng Suo, Yu Gu, Guan Huei See, Arvind Sundarrajan
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Publication number: 20210202334Abstract: A method of forming a semiconductor structure on a wafer includes depositing a polymer layer on the wafer in a wafer-level packaging process, forming at least one wafer-level packaging structure in the polymer layer using a direct writing process that alters a chemical property of portions of the polymer layer that have been directly written to, and removing portions of the polymer layer that have not been written to by the direct writing process revealing the at least one wafer-level packaging structure. In some embodiments, the direct writing process is a two-photon polymerization process that uses a femtosecond laser in combination with a pair of galvanometric laser scanners to solidify portions of the polymer layer to form the wafer-level packaging structure.Type: ApplicationFiled: December 31, 2019Publication date: July 1, 2021Inventors: PENG SUO, PRAYUDI LIANTO, GUAN HUEI SEE, ARVIND SUNDARRAJAN, LIT PING LAM, PANGYEN ONG, OLIVIA KOENTJORO, WEI-SHENG LEI, JUNGRAE PARK
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Publication number: 20200306931Abstract: Methods and apparatus for removing particles from a substrate surface after a chemical mechanical polish. In some embodiments, the apparatus may include a manifold configured to receive and atomize a fluid and at least one spray nozzle mounted to the manifold and configured to spray the atomized fluid in a divergent spray pattern such that the substrate surface is cleansed when impinged by spray from the at least one spray nozzle, wherein the at least one spray nozzle sprays the atomized fluid at a pressure of approximately 30 psi to approximately 2500 psi.Type: ApplicationFiled: March 25, 2019Publication date: October 1, 2020Inventors: PRAYUDI LIANTO, PENG SUO, SHIH-CHAO HUNG, PIN GIAN GAN, CHUN YU TO, PERIYA GOPALAN, KOK SEONG TEO, LIT PING LAM, ANDY LOO, PANGYEN ONG, DAVID P. SURDOCK, KEITH YPMA, BRIAN WILLIAMS, SCOTT OSTERMAN, MARVIN L. BERNT, MUHAMMAD NORHAZWAN, SAMUEL GOPINATH, MUHAMMAD AZIM, GUAN HUEI SEE, QI JIE PENG, SRISKANTHARAJAH THIRUNAVUKARASU, ARVIND SUNDARRAJAN
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Patent number: 10636696Abstract: A method of processing a substrate includes depositing a layer of uncured polymer material atop a substrate to cover an exposed conductive layer on the substrate, exposing at least one area of the layer using a photolithography process, developing the layer in the photolithography process to remove a first portion of uncured polymer material from the at least one area, etching the layer with a dry etch process to remove a second portion of uncured polymer material from the at least one area to expose a top surface of the conductive layer and form a via in the layer, and curing the layer to form a cured polymer material.Type: GrantFiled: January 18, 2019Date of Patent: April 28, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Yu Gu, Guan Huei See, Peng Suo, Prayudi Lianto, Arvind Sundarrajan
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Patent number: 10475735Abstract: Methods of processing a substrate include: providing a substrate with a first polymer dielectric layer; forming a first RDL on the first polymer dielectric layer; constructing a 3D MIM capacitive stack on the first RDL in at least one opening in a top surface of a second polymer dielectric layer, the 3D MIM capacitive stack having a top electrode, a bottom electrode, and a capacitive dielectric layer interposed between the top electrode and the bottom electrode; depositing a dielectric layer on the 3D MIM capacitive stack and on the second polymer dielectric layer; and removing a portion of the dielectric layer to expose at least a portion of the top electrode at a bottom of at least one opening of the 3D MIM capacitive stack and to expose at least a portion of the metal layer at a bottom of at least one opening of the second polymer dielectric layer.Type: GrantFiled: June 15, 2017Date of Patent: November 12, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Peng Suo, Guan Huei See, Arvind Sundarrajan
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Publication number: 20190287898Abstract: Methods and apparatus for forming an embedded antifuse in a wafer-level packaging compatible process. In some embodiments, a method for forming an embedded antifuse includes forming a first redistribution layer on a first polymer layer, depositing an antifuse dielectric layer on the first redistribution layer, forming a second polymer layer on the antifuse dielectric layer, creating at least one first via through the second polymer layer to the antifuse dielectric layer using a lithography process with, for example, a dielectric etch, and forming a second redistribution layer on the second polymer layer and contacting the antifuse dielectric layer at a bottom of the at least one first via.Type: ApplicationFiled: March 8, 2019Publication date: September 19, 2019Inventors: PENG SUO, YU GU, GUAN HUEI SEE, ARVIND SUNDARRAJAN
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Publication number: 20190051454Abstract: A method of forming a magnetic core on a substrate having a stacked inductor coil includes etching a plurality of polymer layers to form at least one feature through the plurality of polymer layers, wherein the at least one feature is disposed within a central region of a stacked inductor coil formed on the substrate; and depositing a magnetic material within the at least one feature.Type: ApplicationFiled: August 7, 2018Publication date: February 14, 2019Inventors: Peng Suo, Yu Gu, Guan Huei See, Arvind Sundarrajan
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Publication number: 20190051596Abstract: Methods of processing a substrate include providing a substrate having a polymer dielectric layer and a metal layer formed atop the polymer dielectric layer; depositing a plurality of polymer layers atop the substrate; patterning the plurality of polymer layers to form at least one via that extends from a top surface of an uppermost polymer layer to a top surface of the metal layer; and forming a three-dimensional metal-insulator-metal (3D MIM) capacitance stack in the at least one via and over a portion of the metal layer and the plurality of polymer layers.Type: ApplicationFiled: August 10, 2017Publication date: February 14, 2019Inventors: Peng Suo, Yu Gu, Guan Huei See, Arvind Sundarajan
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Publication number: 20180366401Abstract: Methods of processing a substrate include: providing a substrate with a first polymer dielectric layer; forming a first RDL on the first polymer dielectric layer; constructing a 3D MIM capacitive stack on the first RDL in at least one opening in a top surface of a second polymer dielectric layer, the 3D MIM capacitive stack having a top electrode, a bottom electrode, and a capacitive dielectric layer interposed between the top electrode and the bottom electrode; depositing a dielectric layer on the 3D MIM capacitive stack and on the second polymer dielectric layer; and removing a portion of the dielectric layer to expose at least a portion of the top electrode at a bottom of at least one opening of the 3D MIM capacitive stack and to expose at least a portion of the metal layer at a bottom of at least one opening of the second polymer dielectric layer.Type: ApplicationFiled: June 15, 2017Publication date: December 20, 2018Inventors: Peng Suo, Guan Huei See, Arvind Sundarrajan