Abstract: Aspects of the disclosure are directed to a method for use on a blockchain network that includes an accounting node subnetwork having accounting nodes configured to record a data block onto a blockchain and a service node having service nodes configured to verify data blocks recorded by the accounting nodes onto the blockchain. The method can include generating a signature based on transaction information to be included in a data block to be added onto the blockchain by using a key specific to the accounting node. The method can further include adding the transaction information and the generated signature to the data block and adding the data block onto the blockchain, and transmitting the signature to the service nodes in the service node subnetwork, so that the service nodes perform signature verification on the signature based on the key specific to the accounting node.

Abstract: Disclosed are a backlight module and a display panel. The backlight module has a plurality of light-emitting unit groups. Each of the light-emitting unit groups has a plurality of light-emitting units. The plurality of light-emitting units are arranged in an array.

Abstract: A display panel and a display device are provided. The display panel includes a plurality of independent display areas. Pixels in each of the display areas are respectively driven to display by at least one source drive circuit, and the source drive circuits that drive each of the display areas are electrically insulated. The present disclosure realizes that the display panel has the characteristics of high resolution and large size.

Abstract: The embodiment of the present disclosure provides an anti-interference method and apparatus for touch signal. When scanning the touch signal, increasing the scanning frequency of the touch drive circuit to obtain more touch signal data corresponding to interference, and then comparing and removing the abnormal touch signal data, and outputting the finally sifted touch signal data to achieve the purpose of improving the touch effect of the touch screen and the accuracy of the touch screen reported point.

Abstract: A neural network training method, apparatus, a storage medium, and a computer device are provided. The method includes: obtaining a training sample set, each training sample including a standard label; inputting the each training sample into a neural network model including n attention networks, the n attention networks respectively mapping the each training sample to n subspaces, each of the n subspaces including a query vector sequence, a key vector sequence, and a value vector sequence; calculating a space difference degree between the n subspaces by using the neural network model; calculating an output similarity degree according to an output of the neural network model and the standard label corresponding to the each training sample; and adjusting a model parameter of the neural network model according to the space difference degree and the output similarity degree until a convergence condition is satisfied to obtain a target neural network model.

Abstract: Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.

Abstract: Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.

Abstract: A two-liquid process for synthesizing polyurethane with high heat-resistance and high abrasion-resistance is disclosed, which utilizes a semi-reactive polymer A solution containing hydroxyl groups and a semi-reactive polymer B solution containing poly-isocyanate groups. The polymer A and B solution are mixed for performing a second reaction and then coated on a substrate by a coating machine, and the coating layer is cured to form a polyurethane film. The semi-reactive polymer A and B solution are pre-polymerized in advance. The required polyurethane resin expands on the semi-reactive polymer A and B with a whole range of new functionality and construction styles through polymerization to produce high heat-resistant and high abrasion-resistant polyurethane film through coating facility under the working temperature about 80° C. A fabric is coupled during coating step for polyurethane leather. The two-liquid process is without using solvent as carrier.

Abstract: A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

Abstract: A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.

Abstract: A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.

Abstract: A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

Abstract: A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

Abstract: A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

Abstract: A method, system, and computer product uses a hashed static single assignment (SSA) form as a program representation and a medium for performing global scalar optimization. A compiler, after expressing the computer program in SSA form, can perform one or more static single assignment (SSA)-based, SSA-preserving global scalar optimization procedures on the SSA representation. Such a procedure modifies, (i.e., optimizes) the SSA representation of the program while preserving the utility of its embedded use-deprogram information for purposes of subsequent SSA-based, SSA-preserving global scalar optimizations. This saves the overhead expense of having to explicitly regenerate use-def program information for successive SSA-based, SSA-preserving global scalar optimizations.

Abstract: A method, system, and computer program product for performing register promotion, that optimizes placement of load and store operations of a computer program within a compiler. Based on the observation that the circumstances for promoting a memory location's value to register coincide with situations where the program exhibits partial redundancy between accesses to the memory location, the system is an approach to register promotion that models the optimization as two separate problems: (1) the partial redundancy elimination (PRE) of loads and (2) the PRE of stores. Both of these problems are solved through a sparse approach to PRE. The static single assignment PRE (SSAPRE) method for eliminating partial redundancy using a sparse SSA representation representations the foundation in eliminating redundancy among memory accesses, enabling the achievement of both computational and live range optimality in register promotion results.

Abstract: Partial redundancy elimination of a computer program is described that operates using a static single assignment (SSA) representation of a computer program. The SSA representation of the computer program is processed to eliminate partially redundant expressions in the computer program. This processing involves inserting .PHI. functions for expressions where different values of the expressions reach common points in the computer program. A result of each of the .PHI. functions is stored in a hypothetical variable h. The processing also involves a renaming step where SSA versions are assigned to hypothetical variables h in the computer program, a down safety step of determining whether each .PHI. function in the computer program is down safe, and a will be available step of determining whether each expression in the computer program will be available at each .PHI. function following eventual insertion of code into the computer program for purposes of partial redundancy elimination.