Abstract: In certain aspects, a method for controlling wafer stress is disclosed. A semiconductor film is formed on a backside of a wafer. The wafer is deformed by stress associated with a front-side semiconductor structure on a front side of the wafer opposite to the backside of the wafer. A laser application region of the semiconductor film is determined. A laser anneal process is performed in the laser application region of the semiconductor film.

Abstract: The present disclosure discloses a three-dimensional (3D) memory, which includes a peripheral wafer and an array wafer. The peripheral wafer includes a first peripheral structure and a second peripheral structure. The array wafer includes a substrate, a structure to be tested and multiple interconnecting portions. The substrate includes a first well region and a second well region. The array wafer includes the structure to be tested which has a first connecting portion, a second connecting portion, and multiple interconnecting portions. The first peripheral structure is connected to the first well region and the first connecting portion of the structure to be tested by the first interconnecting portion and the second interconnecting portion respectively. The second peripheral structure is connected to the second well region and the second connecting portion of the structure to be tested by the third interconnecting portion and the fourth interconnecting portion respectively.

Abstract: In certain aspects, a method for controlling wafer stress is disclosed. A semiconductor film is formed on a backside of a wafer. The wafer is deformed by stress associated with a front-side semiconductor structure on a front side of the wafer opposite to the backside of the wafer. A laser application region of the semiconductor film is determined. A laser anneal process is performed in the laser application region of the semiconductor film.