Patents by Inventor Per Broms
Per Broms has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11190028Abstract: A battery management system having configurable batteries is disclosed. The battery management system generally includes (a) one or more cell control units, each cell control unit configured to control and/or balance a charge in a plurality of battery cells, and (b) a master controller in electrical communication with cell control unit(s). The cell control unit(s) as a whole include one or more switches, configured to be electrically connected to a first battery cell of a plurality of battery cells, and a resistor, a capacitor or an inductor electrically (i) connected to one switch and (ii) connected or connectable to a second battery cell. The master controller is configured to open or close each switch. The configurable battery generally includes a plurality of battery cells and switches configured to connect or disconnect the plurality of battery cells in a configurable or predetermined manner.Type: GrantFiled: August 16, 2019Date of Patent: November 30, 2021Assignee: Ensurge Micropower ASAInventors: Christer Karlsson, Per Broms
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Publication number: 20200059106Abstract: A battery management system having and configurable batteries are disclosed. The battery management system generally includes (a) one or more cell control units, each configured to control and/or balance a charge in a plurality of battery cells, and (b) a master controller in electrical communication with cell control unit(s). The cell control unit(s) as a whole include one or more switches, configured to be electrically connected to a first one of a plurality of battery cells, and a resistor, capacitor or inductor electrically (i) connected to one switch and (ii) connected or connectable to a second battery cell. The master controller is configured to open or close each switch. The configurable battery generally includes a plurality of battery cells and switches configured to connect or disconnect the battery cells in a configurable or predetermined manner.Type: ApplicationFiled: August 16, 2019Publication date: February 20, 2020Applicant: Thin Film Electronics ASAInventors: Christer KARLSSON, Per BRÖMS
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Patent number: 10453853Abstract: A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (?L) occurring in the protective layer (11) and thus preventing said dimensional change (?L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.Type: GrantFiled: July 28, 2016Date of Patent: October 22, 2019Assignee: THIN FILM ELECTRONICS ASAInventors: Christer Karlsson, Olle Jonny Hagel, Jakob Nilsson, Per Bröms
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Patent number: 9934836Abstract: An electronic component (1) and an electronic device (100) comprising one or more such components (1). The electronic component (1) comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one insulating or semi-insulating layer (7) between said electrodes. The stack further comprises a buffer layer (13), arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (?L) occurring in the protective layer (11) and thus preventing said dimensional change (?L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.Type: GrantFiled: June 21, 2012Date of Patent: April 3, 2018Assignee: THIN FILM ELECTRONICS ASAInventors: Christer Karlsson, Olle Jonny Hagel, Jakob Nilsson, Per Bröms
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Publication number: 20160336334Abstract: A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (?L) occurring in the protective layer (11) and thus preventing said dimensional change (?L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Inventors: Christer Karlsson, Olle Jonny Hagel, Jakob Nilsson, Per Bröms
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Patent number: 9412705Abstract: A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (?L) occurring in the protective layer (11) and thus preventing said dimensional change (?L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.Type: GrantFiled: June 27, 2011Date of Patent: August 9, 2016Assignee: Thin Film Electronics ASAInventors: Christer Karlsson, Olle Jonny Hagel, Jakob Nilsson, Per Bröms
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Publication number: 20160095226Abstract: A printed timer label including a substrate, a printed battery on the substrate, a printed load resistance configured to control a discharge time of the printed battery, and printed voltage comparison circuitry connected to the printed battery and configured to provide an output signal depending on the output voltage of the printed battery relative to a predetermined threshold value.Type: ApplicationFiled: September 30, 2015Publication date: March 31, 2016Applicant: THIN FILM ELECTRONICS ASAInventors: Per BRÖMS, Robert FORCHHEIMER
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Publication number: 20140216791Abstract: An electronic component (1) and an electronic device (100) comprising one or more such components (1). The electronic component (1) comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one insulating or semi-insulating layer (7) between said electrodes. The stack further comprises a buffer layer (13), arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (?L) occurring in the protective layer (11) and thus preventing said dimensional change (?L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.Type: ApplicationFiled: June 21, 2012Publication date: August 7, 2014Applicant: THIN FILM ELECTRONICS ASAInventors: Christer Karlsson, Olle Jonny Hagel, Jakob Nilsson, Per Bröms
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Publication number: 20140210026Abstract: A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (?L) occurring in the protective layer (11) and thus preventing said dimensional change (?L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.Type: ApplicationFiled: June 27, 2011Publication date: July 31, 2014Applicant: THIN FILM ELECTRONICS ASAInventors: Christer Karlsson, Olle Jonny Hagel, Jakob Nilsson, Per Bröms
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Patent number: 8184467Abstract: In a non-volatile electric memory system a memory unit and a read/write unit are provided as physically separate units. The memory unit is based on a memory material that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrodes and/or contacts are either provided in the memory unit or in the read/write unit and contacts are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected. The memory material of the memory unit can be polarized into two discernible polarization states.Type: GrantFiled: June 8, 2006Date of Patent: May 22, 2012Assignee: Thin Film Electronics ASAInventors: Per Bröms, Christer Karlsson, Geirr I. Leistad, Per Hamberg, Staffan Björklid, Johan Carlsson, Göran Gustafsson, Hans Gude Gudesen
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Patent number: 7764529Abstract: In a non-volatile electric memory system a card-like memory unit (10) and a read/write unit (11) are provided as physically separate units. The memory unit (10) is based on a memory material (4) that can be set to at least two distinct physical states by applying an electric field across the memory material. The read/write unit (10) comprises contact means (9) provided in a determined geometrical pattern enabling a definition of memory cells in memory unit (10) in an initial write operation, the memory cells being located in a geometrical pattern corresponding to that of the contact means (9). Establishing a physical contact between the memory unit (10) and the read/write unit (11) closes an electrical circuit over an addressed memory cell such that read, write or erase operations can be effected.Type: GrantFiled: June 8, 2006Date of Patent: July 27, 2010Assignee: Thin Film Electronics ASAInventors: Geirr I. Leistad, Per Broms, Christer Karlsson
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Publication number: 20080198644Abstract: In a non-volatile electric memory system a memory unit (4) and a read/write unit (11) are provided as physically separate units. The memory unit (10) is based on a memory material (4) that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrode means and/or contact means are either provided in the memory unit or in the read/write unit and contact means are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Contact means in the read/write unit are provided connectable to driving, sensing and control means located in the read/write unit or in an external device connected with the latter. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected.Type: ApplicationFiled: June 8, 2006Publication date: August 21, 2008Applicant: Thin Film Electronics ASAInventors: Per Broms, Christer Karlsson, Geirr I. Leistad, Per Hamberg, Staffan Bjorklid, Johan Carlsson, Goran Gustafsson, Hans Gude Gudesen
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Publication number: 20080198640Abstract: In a non-volatile electric memory system a card-like memory unit (10) and a read/write unit (11) are provided as physically separate units. The memory unit (10) is based on a memory material (4) that can be set to at least two distinct physical states by applying an electric field across the memory material. The read/write unit (10) comprises contact means (9) provided in a determined geometrical pattern enabling a definition of memory cells in memory unit (10) in an initial write operation, the memory cells being located in a geometrical pattern corresponding to that of the contact means (9). Establishing a physical contact between the memory unit (10) and the read/write unit (11) closes an electrical circuit over an addressed memory cell such that read, write or erase operations can be effected.Type: ApplicationFiled: June 8, 2006Publication date: August 21, 2008Inventors: Geirr I. Leistad, Per Broms, Christer Karlsson
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Patent number: 7248524Abstract: In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.Type: GrantFiled: June 29, 2005Date of Patent: July 24, 2007Assignee: Thin Film Electronics ASAInventors: Per-Erik Nordal, Geirr I. Leistad, Per Bröms, Hans Gude Gudesen
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Publication number: 20060007722Abstract: In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.Type: ApplicationFiled: June 29, 2005Publication date: January 12, 2006Applicant: Thin Film Electronics ASAInventors: Per-Erik Nordal, Geirr Leistad, Per Broms, Hans Gudesen
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Patent number: 6982895Abstract: A passive matrix-addressable device may include individually addressable cells of a polarizable material. The cells store data in one of two polarization states in each cell, and the polarization states in the cells are written and read by addressing via electrodes which form word and bit lines. The cells are provided in or at the crossings between the word and bit lines and a voltage pulse protocol is used read and write data to cells. During reading, a word line is activated by applying voltage which relative to the potential on all crossing bit lines corresponds to the voltage Vs and data stored in the cells connected to this active word line are determined by detecting the charge values of the cells.Type: GrantFiled: November 7, 2002Date of Patent: January 3, 2006Assignee: Thin Film Electronics ASAInventors: Per Bröms, Christer Karlsson
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Patent number: 6937500Abstract: A matrix-addressable ferroelectric or electret memory device and a method of operating are explained. The method includes applying a first plurality of voltage difference across a first and a second set of electrodes in the memory when data are read, and applying a second plurality of voltage differences when data are refreshed or rewritten. The first and second plurality of voltage differences correspond to sets of potential levels comprising time sequences of voltage pulses. At least one parameter indicative of a change in a memory cell response is used for determining at least one correction factor for the voltage pulses, whereby the pulse parameter is adjusted accordingly. The memory device comprises means for determining the at least one parameter, a calibration memory connected with means for determining the correction factor, and control circuits for adjusting pulse parameters as applied to read and write operations in the memory device.Type: GrantFiled: September 11, 2003Date of Patent: August 30, 2005Assignee: Thin Film Electronics ASAInventors: Hans Gude Gudesen, Per-Erik Nordal, Geirr I. Leistad, Per Bröms, Per Sandström, Mats Johansson
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Publication number: 20050073869Abstract: A matrix-addressable ferroelectric or electret memory device and a method of operating are explained. The method includes applying a first plurality of voltage difference across a first and a second set of electrodes in the memory when data are read, and applying a second plurality of voltage differences when data are refreshed or rewritten. The first and second plurality of voltage differences correspond to sets of potential levels comprising time sequences of voltage pulses. At least one parameter indicative of a change in a memory cell response is used for determining at least one correction factor for the voltage pulses, whereby the pulse parameter is adjusted accordingly. The memory device comprises means for determining the at least one parameter, a calibration memory connected with means for determining the correction factor, and control circuits for adjusting pulse parameters as applied to read and write operations in the memory device.Type: ApplicationFiled: September 11, 2003Publication date: April 7, 2005Inventors: Hans Gudesen, Per-Erik Nordal, Geirr Leistad, Per Broms, Per Sandstrom, Mats Johansson
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Patent number: 6606261Abstract: A method and apparatus for performing read and write operations in matrix-addressed memory array of memory cells is described. The memory cells comprising an electrically polarizable material exhibiting polarization remanence, in particular and electret or ferroelectric material, where a logical value stored in a memory cell is represented by an actual polarization state in the memory cell. The degree of polarization in the polarizable material is limited during each read and write cycle to a value defined by a circuit device controlling the read and write operations, with said value ranging from zero to an upper limit corresponding to saturation of the polarization and consistent with predetermined criterta for a reliable detection of a logic state of a memory cell.Type: GrantFiled: July 6, 2001Date of Patent: August 12, 2003Assignee: Thin Film Electronics ASAInventors: Hans Gude Gudesen, Per-Erik Nordal, Per Bröms, Mats Johansson
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Publication number: 20030103386Abstract: In a method for reading of a passive matrix-addressable device, particularly a memory device or a sensor device with individually addressable cells of a polarizable material, the cells store data in the form of one of two polarization states +Pr;−Pr in each cell, and the polarization states in the cells are written and read by addressing via electrodes which form word and bit lines (WL;BL) in an orthogonal electrode matrix, and wherein the cells are provided in or at the crossings between the word and bit lines (WL;BL) a voltage pulse protocol is used according to which electric potentials on all word and bit lines are controlled coordinated in time. During reading a word line (WL) is activated by applying voltage which relative to the potential on all crossing bit lines (BL) corresponds to the voltage Vs and data stored in the cells connected to this active word line (AWL) are determined by detecting the charge values of the cells in a detection means (SA).Type: ApplicationFiled: November 7, 2002Publication date: June 5, 2003Inventors: Per Broms, Christer Karlsson