Abstract: A handshake circuit portion for performing a handshake procedure to facilitate data reception by an associated circuit portion is provided. The handshake circuit portion comprises a request signal input for detecting a request signal from a further handshake circuit portion associated with a further circuit portion, an acknowledge signal output for asserting an acknowledge signal for the further handshake circuit portion, and a blocking signal input for detecting a blocking signal from the associated circuit portion. The handshake circuit portion is arranged to detect a request signal via the request signal input, determine if a blocking signal is present on the blocking signal input, and if a blocking signal is not present on the blocking signal input, respond to the request signal by asserting an acknowledge signal via the acknowledge signal output.

Abstract: An integrated-circuit device comprises first and second peripherals, connected to a processor via a bus system, a peripheral interconnect that is separate from the bus system, wake up logic, a configuration memory and a power controller. In response to a change of state, the first peripheral generates event signals that are output to the peripheral interconnect. The peripheral interconnect provides the event signal to the second peripheral, which initiates tasks in response. The first peripheral, second peripheral and the wake-up logic are in a first, second and third power domain respectively. The power controller provides power to the third power domain whenever the first or second power domain is powered up. The wake-up logic detects an event signal from the first peripheral and, if it determines that the second peripheral is configured to initiate a task in response, it instructs the power controller to power up the second peripheral.

Abstract: An integrated-circuit device comprises first and second peripherals, connected to a processor via a bus system, a peripheral interconnect that is separate from the bus system, wake up logic, a configuration memory and a power controller. In response to a change of state, the first peripheral generates event signals that are output to the peripheral interconnect. The peripheral interconnect provides the event signal to the second peripheral, which initiates tasks in response, The first peripheral, second peripheral and the wake-up logic are in a first, second and third power domain respectively. The power controller provides power to the third power domain whenever the first or second power domain is powered up. The wake-up logic detects an event signal from the first peripheral and, if it determines that the second peripheral is configured to initiate a task in response, it instructs the power controller to power up the second peripheral.

Abstract: A serial, half-duplex start/stop event detection circuit comprises a stop detection flip-flop clocked by a serial data input that takes a serial clock input as an input and generates a stop signal output indicative of a stop event. A start detection flip-flop, clocked by an inverted copy of the serial data input, takes the serial clock input as an input and generates a start signal output indicative of a start event. A first buffer flip-flop, clocked by an inverted copy of the serial clock input, takes the start signal output as an input and generates a first delayed start signal output. Similarly, a second buffer flip-flop, clocked by the serial clock input, takes the first delayed start signal output as an input and generates a second delayed start signal output. The second delayed start signal output resets at least one of said stop detection, start detection or first buffer flip-flops.

Abstract: An arrangement for transferring a data signal (data_a) from a first clock domain (2) to a second clock domain (4) in a digital system. The arrangement has a signal input (6, 7) for receiving an input signal (data_a) from the first clock domain (2), means (6, 7) for storing the input signal (data_a), and means (12, 13) for transferring the input signal (data_a) to the second clock domain (4) following a transition in the clock signal (ck) of the second clock domain (4).

Abstract: A serial, half-duplex start/stop event detection circuit comprises a stop detection flip-flop clocked by a serial data input that takes a serial clock input as an input and generates a stop signal output indicative of a stop event. A start detection flip-flop, clocked by an inverted copy of the serial data input, takes the serial clock input as an input and generates a start signal output indicative of a start event. A first buffer flip-flop, clocked by an inverted copy of the serial clock input, takes the start signal output as an input and generates a first delayed start signal output. Similarly, a second buffer flip-flop, clocked by the serial clock input, takes the first delayed start signal output as an input and generates a second delayed start signal output. The second delayed start signal output resets at least one of said stop detection, start detection or first buffer flip-flops.

Abstract: An arrangement for transferring a data signal (data_a) from a first clock domain (2) to a second clock domain (4) in a digital system. The arrangement has a signal input (6, 7) for receiving an input signal (data_a) from the first clock domain (2), means (6, 7) for storing the input signal (data_a), and means (12, 13) for transferring the input signal (data_a) to the second clock domain (4) following a transition in the clock signal (ck) of the second clock domain (4).

Abstract: A serial interface comprises a clock line, a request line, a ready line, a master-to-slave data line, and a slave-to-master data line. A master device transmits a clock signal to a slave device over the clock line. In a first transaction, the master device sends a master transmission request signal to the slave device over the request line; in response, the slave device sends a slave transmission accept signal over the ready line, which causes the master device to transmit binary data to the slave device over the master-to-slave data line. In a second transaction, the slave device sends a slave transmission request signal over the ready line; in response, the master device sends a master transmission accept signal over the request line, which causes the slave device to transmit binary data to the master device over the slave-to-master data line. In at least one of the transactions, the master and slave devices transmit binary data at the same time as each other.

Abstract: A temperature sensing device for an integrated circuit comprises an oscillator (2) having a characteristic frequency dependent on the temperature and a digital counter (16) arranged to count a number of pulses generated by the oscillator (2) in a given time interval, or the time taken for the oscillator to generate a given number of pulses. Either of these gives a measured value. The device is configured to use a difference between the measured value and a stored reference value in a linearisation algorithm to estimate a temperature.

Abstract: A serial interface comprises a clock line, a request line, a ready line, a master-to-slave data line, and a slave-to-master data line. A master device transmits a clock signal to a slave device over the clock line. In a first transaction, the master device sends a master transmission request signal to the slave device over the request line; in response, the slave device sends a slave transmission accept signal over the ready line, which causes the master device to transmit binary data to the slave device over the master-to-slave data line. In a second transaction, the slave device sends a slave transmission request signal over the ready line; in response, the master device sends a master transmission accept signal over the request line, which causes the slave device to transmit binary data to the master device over the slave-to-master data line. In at least one of the transactions, the master and slave devices transmit binary data at the same time as each other.