Abstract: A computing system comprises a processor, a data storage unit, and a block size table (BST). The processor includes at least one cache configured to store data. The data storage unit is configured to store data in a compressed format in fixed size units. The BST is configured to store block size entries corresponding to data blocks stored in the data storage unit. In response to a miss in the cache corresponding to a target data block, the processor is configured to identify an entry in the BST corresponding to the target data block, utilize information stored in the entry to determine the location of the target data block in the data storage unit, and cause the target data block to be retrieved from the data storage unit, decompressed, and stored in the cache.

Abstract: In one embodiment, a cache comprises a cache memory and a cache control circuit coupled to the cache memory. The cache memory is configured to store a plurality of cache blocks and a plurality of cache states. Each of the plurality of cache states corresponds to a respective one of the plurality of cache blocks. The cache control circuit is configured to implement a cache coherency protocol that includes a plurality of stable states and a transient state The transient state may be used in response to any request from a local consumer if completing the request includes a change between the plurality of stable states and making the change includes transmitting at least a first communication to maintain coherency on an interconnect.

Abstract: A coherence prediction mechanism includes a history cache for storing a plurality of cache entries each storing coherence history information for a corresponding block of data. Entries in the history cache are used to index into a pattern memory containing coherence predictions.