Patents by Inventor Per Stenström

Per Stenström has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180143770
    Abstract: Methods, devices and systems enhance compression and decompression of data values when they comprise a plurality of semantically meaningful data fields. According to a first inventive concept of the present invention disclosure, compression is not applied to each data value as a whole, but instead to at least one of the semantically meaningful data fields of each data value, and in isolation from the other ones. A second inventive concept organizes the data fields that share the same semantic meaning together to accelerate compression and decompression as multiple compressors and decompressors can be used in parallel. A third inventive concept is a system where methods and devices are tailored to perform compression and decompression of the semantically meaningful data fields of floating-point numbers after first partitioning further at least one of said data fields into two or a plurality of sub-fields to increase the degree of value locality and improve compressibility of floating-point values.
    Type: Application
    Filed: May 20, 2016
    Publication date: May 24, 2018
    Inventors: Angelos Arelakis, Per Stenström
  • Publication number: 20180138921
    Abstract: Methods, devices and systems enhance compression and decompression of data blocks of data values by selecting the best suited compression method and device among two or a plurality of compression methods and devices, which are combined together and which said compression methods and devices compress effectively data values of particular data types; said best suited compression method and device is selected using as main selection criterion the dominating data type in a data block by predicting the data types within said data block.
    Type: Application
    Filed: May 20, 2016
    Publication date: May 17, 2018
    Inventors: Angelos Arelakis, Per Stenström
  • Patent number: 9619301
    Abstract: A method of operating a multi-core processor. In one embodiment, each processor core is provided with its own private cache and the device comprises or has access to a common memory, and the method comprises executing a processing thread on a selected first processor core, and implementing a normal access mode for executing an operation within a processing thread and comprising allocating sole responsibility for writing data to given blocks of said common memory, to respective processor cores. The method further comprises implementing a speculative execution mode switchable to override said normal access mode. This speculative execution mode comprises, upon identification of said operation within said processing thread, transferring responsibility for performing said operation to a plurality of second processor cores, and optionally performing said operation on the first processor core as well.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: April 11, 2017
    Assignee: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Andras Vajda, Per Stenström
  • Patent number: 9330001
    Abstract: In one embodiment, a computer cache is extended with structures that can (1) establish the frequency by which distinct values occur in the cache and use that information to (2) compress values in caches into dense codes using a plurality of statistical-based compression techniques and (3) decompress densely coded values to realize caches that can store information densely that can be retrieved with low overhead.
    Type: Grant
    Filed: May 18, 2013
    Date of Patent: May 3, 2016
    Assignee: ZEROPOINT TECHNOLOGIES AB
    Inventors: Angelos Arelakis, Per Stenström
  • Publication number: 20140033217
    Abstract: A method of operating a multi-core processor. In one embodiment, each processor core is provided with its own private cache and the device comprises or has access to a common memory, and the method comprises executing a processing thread on a selected first processor core, and implementing a normal access mode for executing an operation within a processing thread and comprising allocating sole responsibility for writing data to given blocks of said common memory, to respective processor cores. The method further comprises implementing a speculative execution mode switchable to override said normal access mode. This speculative execution mode comprises, upon identification of said operation within said processing thread, transferring responsibility for performing said operation to a plurality of second processor cores, and optionally performing said operation on the first processor core as well.
    Type: Application
    Filed: April 5, 2012
    Publication date: January 30, 2014
    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Andras Vajda, Per Stenström
  • Publication number: 20130311722
    Abstract: In one embodiment, a computer cache is extended with structures that can (1) establish the frequency by which distinct values occur in the cache and use that information to (2) compress values in caches into dense codes using a plurality of statistical-based compression techniques and (3) decompress densely coded values to realize caches that can store information densely that can be retrieved with low overhead.
    Type: Application
    Filed: May 18, 2013
    Publication date: November 21, 2013
    Inventors: Angelos Arelakis, Per Stenström