Patents by Inventor Periannan R. Chidambaram

Periannan R. Chidambaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8846487
    Abstract: A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: September 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Angelo Pinto, Periannan R. Chidambaram, Rick L. Wise
  • Publication number: 20130029471
    Abstract: A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 31, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Angelo Pinto, Periannan R. Chidambaram, Rick L. Wise
  • Publication number: 20100304547
    Abstract: A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.
    Type: Application
    Filed: December 14, 2009
    Publication date: December 2, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Angelo Pinto, Periannan R. Chidambaram, Rick L. Wise
  • Publication number: 20090057816
    Abstract: A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 5, 2009
    Inventors: Angelo Pinto, Periannan R. Chidambaram, Rick L. Wise
  • Patent number: 7179696
    Abstract: A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure (114). Source and drain regions (140, 142) are then formed (26) within the semiconductor substrate (102) on opposing sides of the channel (122) with a phosphorus dopant.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: February 20, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Srinivasan Chakravarthi, Periannan R. Chidambaram