Abstract: The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.

Abstract: Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.

Abstract: An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. The page table walk can include using a controller coupled to the array. The controller can be configured to operate the sensing circuitry to determine a physical address of a portion of data by accessing the page table in the array of memory cells. The controller can be configured to operate the sensing circuitry to cause storing of the portion of data in a buffer.

Abstract: The present disclosure includes apparatuses and methods for operations using compressed and decompressed data. An example method includes receiving compressed data to a processing in memory (PIM) device and decompressing the compressed data on the PIM device.

Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

Abstract: An example apparatus includes a processing in memory (PIM) capable device having an array of memory cells and sensing circuitry coupled to the array, where the sensing circuitry includes a sense amplifier and a compute component. The PIM capable device includes timing circuitry selectably coupled to the sensing circuitry. The timing circuitry is configured to control timing of performance of compute operations performed using the sensing circuitry. The PIM capable device also includes a sequencer selectably coupled to the timing circuitry. The sequencer is configured to coordinate the compute operations. The apparatus also includes a source external to the PIM capable device. The sequencer is configured to receive a command instruction set from the source to initiate performance of a compute operation.

Abstract: The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.

Abstract: The present disclosure includes apparatuses and methods for in data path compute operations. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array. A plurality of shared input/output (I/O) lines provides a data path. The plurality of shared I/O lines selectably couples a first subrow of a row of the array via the sensing circuitry to a first compute component in the data path to move a first data value from the first subrow to the first compute component and a second subrow of the respective row via the sensing circuitry to a second compute component to move a second data value from the second subrow to the second compute component. An operation is performed on the first data value from the first subrow using the first compute component substantially simultaneously with movement of the second data value from the second subrow to the second compute component.

Abstract: The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The apparatus also includes a controller configured to direct a first movement of a number of data values from a subarray in the second subset to a subarray in the first subset and performance of a sequential plurality of operations in-memory on the number of data values by the first sensing circuitry coupled to the first subset.

Abstract: Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.

Abstract: The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The apparatus also includes a controller configured to direct a first movement of a number of data values from a subarray in the second subset to a subarray in the first subset and performance of a sequential plurality of operations in-memory on the number of data values by the first sensing circuitry coupled to the first subset.

Abstract: Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.

Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

Abstract: An example apparatus includes a processing in memory (PIM) capable device having an array of memory cells and sensing circuitry coupled to the array, where the sensing circuitry includes a sense amplifier and a compute component. The PIM capable device includes timing circuitry selectably coupled to the sensing circuitry. The timing circuitry is configured to control timing of performance of compute operations performed using the sensing circuitry. The PIM capable device also includes a sequencer selectably coupled to the timing circuitry. The sequencer is configured to coordinate the compute operations. The apparatus also includes a source external to the PIM capable device. The sequencer is configured to receive a command instruction set from the source to initiate performance of a compute operation.

Abstract: Apparatuses and methods are provided for processing in memory. An example apparatus includes a processing in memory (PIM) capable device having an array of memory cells and sensing circuitry coupled to the array. The PIM capable includes a row address strobe (RAS) component selectably coupled to the array. The RAS component is configured to select, retrieve a data value from, and input a data value to a specific row in the array. The PIM capable device also includes a RAS manager selectably coupled to the RAS component. The RAS manager is configured to coordinate timing of a sequence of compute sub-operations performed using the RAS component. The apparatus also includes a source external to the PIM capable device. The RAS manager is configured to receive instructions from the source to control timing of performance of a compute operation using the sensing circuitry.

Abstract: Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.

Abstract: Information relating to a user input to edit a portion of an image is received,A where the image is divided into a plurality of tiles. In response to the received information, at least one further tile in a representation of the edit is created. A data structure including entries that link the plurality of tiles and the at least one further tile is created. The at least one further tile with the plurality of tiles are combined to produce an output page that includes the image with the edit applied to the image.

Abstract: The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry and configured to cause the memory device to store debugging code in the array of memory cells and execute instructions to perform logical operations using the sensing circuity. The controller is further configured to receive an indication in the executing instructions to halt a logical operation, and to execute the debugging code on the memory device.

Abstract: The present disclosure includes apparatuses and methods for in data path compute operations. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array. A plurality of shared input/output (I/O) lines provides a data path. The plurality of shared I/O lines selectably couples a first subrow of a row of the array via the sensing circuitry to a first compute component in the data path to move a first data value from the first subrow to the first compute component and a second subrow of the respective row via the sensing circuitry to a second compute component to move a second data value from the second subrow to the second compute component. An operation is performed on the first data value from the first subrow using the first compute component substantially simultaneously with movement of the second data value from the second subrow to the second compute component.

Abstract: The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.