Abstract: A wireless receiver that sorts packets including a packet detector, multiple correlators, and multiple packet processors. Each correlator correlates a received signal according to packet type. Each packet processor processes the received signal according to packet type. A signal power detector may be provided to initially qualify the received signal as containing a packet, and the correlators determine whether a packet is present. The correlators may be configured for sequential or simultaneous correlation. For the simultaneous correlator configuration, a correlation monitor is provided to monitor correlation results to determine if the received signal contains a packet, and if so, to determine packet type. A low SNR packet detector may be provided which correlates the received signal to detect weak packet signals.

Abstract: A wireless receiver that sorts packets including a packet detector, multiple correlators, and multiple packet processors. Each correlator correlates a received signal according to packet type. Each packet processor processes the received signal according to packet type. A signal power detector may be provided to initially qualify the received signal as containing a packet, and the correlators determine whether a packet is present. The correlators may be configured for sequential or simultaneous correlation. For the simultaneous correlator configuration, a correlation monitor is provided to monitor correlation results to determine if the received signal contains a packet, and if so, to determine packet type. A low SNR packet detector may be provided which correlates the received signal to detect weak packet signals.

Abstract: A wireless receiver that sorts packets including a packet detector, multiple correlators, and multiple packet processors. Each correlator correlates a received signal according to packet type. Each packet processor processes the received signal according to packet type. A signal power detector may be provided to initially qualify the received signal as containing a packet, and the correlators determine whether a packet is present. The correlators may be configured for sequential or simultaneous correlation. For the simultaneous correlator configuration, a correlation monitor is provided to monitor correlation results to determine if the received signal contains a packet, and if so, to determine packet type. A low SNR packet detector may be provided which correlates the received signal to detect weak packet signals.

Abstract: A wireless receiver that sorts packets including a packet detector, multiple correlators, and multiple packet processors. Each correlator correlates a received signal according to packet type. Each packet processor processes the received signal according to packet type. A signal power detector may be provided to initially qualify the received signal as containing a packet, and the correlators determine whether a packet is present. The correlators may be configured for sequential or simultaneous correlation. For the simultaneous correlator configuration, a correlation monitor is provided to monitor correlation results to determine if the received signal contains a packet, and if so, to determine packet type. A low SNR packet detector may be provided which correlates the received signal to detect weak packet signals.

Abstract: An FEC scheme for wireless receivers including a symbol detector, a symbol selector, CRC logic and output logic. The detector correlates each digital group of the packet with a symbol family and provides possible symbols and corresponding correlation factors. The selector selects several possible symbols for each digital group having the highest correlation factors. The CRC logic calculates possible CRC values for the packet using combinations of the selected symbols. The output logic evaluates the possible CRC values to determine whether there is a correct symbol combination. The system may include logic that determines a symbol quality (SQ) metric for each digital group based on a difference between the two highest correlation factors. The system may include a rank value filter that selects a predetermined number of second choice symbols based on the SQ metrics. The CRC logic calculates the CRC values using combinations of first and second choice symbols.

Abstract: A direct sequence spread spectrum receiver and method for acquiring radio-frequency signals is provided for acquiring data from signals which have been transmitted in a spread spectrum system. The receiver is capable of receiving short data bursts from transmitters without prior knowledge of the time or location of the transmission and rapidly acquiring the signal before continuing with reliable data demodulation. The system includes one or more antennae for receiving RF signals which may be selectively connected to provide the received signals to the system for processing, a quadrature demodulator for providing I and Q baseband signals to a digital baseband processor which includes A/D converters, dual correlators for despreading the digital I and Q signals, a cartesian to polar converter, a demodulator for demodulating the polar coordinate digital I and Q signals, and a data descrambler for obtaining a serial data stream which may be provided to a serial interface.

Abstract: A digital half-band filter with mutliplications using Wallace trees which have lower bits truncated for reduction in size and with a true/complementer providing saturation compensation together with accumulator overflow compensation by monitoring bits more significant than the output bits.

Abstract: A digital half-band filter with mutliplications using Wallace trees which have lower bits truncated for reduction in size and with a true/complementer providing saturation compensation together with accumulator overflow compensation by monitoring bits more significant than the output bits.

Abstract: An enhanced current mirror circuit includes an auxiliary (by-pass) transducer that is effectively coupled in parallel with the current regulation transistor and the gate voltage of which is controlled by a (doped polysilicon) resistor voltage divider. The components of the voltage divider are configured to compensate for a reduction in the size of the principal current control resistor in the current regulation path of the mirror. The auxiliary current (bypass) control circuit effectively compensates for variations in parameters of the components of the current mirror circuit by controllably regulating (bypassing) current that would otherwise flow through the mirror's current control transistor. The voltage divider network is preferably comprised of a plurality of polysilicon resistor elements the configuration of one of which corresponds to the configuration of the principal current control resistor element. The width of another of the resistor elements of the voltage divider network is relatively large.