Abstract: A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.

Abstract: Described embodiments provide a method of adjusting configurable parameters of at least one linear equalizer in a communication system. A transmitting device applies an input signal to a receiver. The at least one linear equalizer equalizes the input signal. A sampler generates one or more sampled values of the input signal. A data detector digitizes the sampled values of the input signal. At least one error detection module generates an error signal based on one or more of a plurality of sampled values of the input signal and a target value. An adaptation module determines a gradient signal based on a comparison of one or more of the plurality of sampled values of the input signal and one or more of the plurality of values of the error signal. The adaptation module adjusts a transfer function of the at least one linear equalizer based on the determined gradient signal.

Abstract: A receiver has an input and a decision feedback equalizer (DFE). The DFE couples to the receiver input and has at least one tap coefficient. An input signal, having a first amplitude level insufficient to cause significant non-linear distortion in the receiver, is applied to the receiver input. After the DFE adapts to the applied input signal having the first amplitude level by adjusting the at least one tap coefficient, the adaptation process is stopped. Then the at least one tap coefficient is scaled by a factor ? and the amplitude of input signal is adjusted to a second amplitude level greater than the first amplitude level by the scale factor ?. Although the second amplitude level might be sufficient to cause significant non-linear distortion in the receiver, the scaled tap coefficient has the correct values for proper DFE operation in the presence of the non-linear distortion.

Abstract: A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.

Abstract: In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained 1T resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with 1T resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.

Abstract: A receiver has an input and a decision feedback equalizer (DFE). The DFE couples to the receiver input and has at least one tap coefficient. An input signal, having a first amplitude level insufficient to cause significant non-linear distortion in the receiver, is applied to the receiver input. After the DFE adapts to the applied input signal having the first amplitude level by adjusting the at least one tap coefficient, the adaptation process is stopped. Then the at least one tap coefficient is scaled by a factor ? and the amplitude of input signal is adjusted to a second amplitude level greater than the first amplitude level by the scale factor ?. Although the second amplitude level might be sufficient to cause significant non-linear distortion in the receiver, the scaled tap coefficient has the correct values for proper DFE operation in the presence of the non-linear distortion.

Abstract: In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained IT resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with IT resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.

Abstract: Described embodiments provide a method of adjusting configurable parameters of at least one linear equalizer in a communication system. A transmitting device applies an input signal to a receiver. The at least one linear equalizer equalizes the input signal. A sampler generates one or more sampled values of the input signal. A data detector digitizes the sampled values of the input signal. At least one error detection module generates an error signal based on one or more of a plurality of sampled values of the input signal and a target value. An adaptation module determines a gradient signal based on a comparison of one or more of the plurality of sampled values of the input signal and one or more of the plurality of values of the error signal. The adaptation module adjusts a transfer function of the at least one linear equalizer based on the determined gradient signal.

Abstract: Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.

Abstract: Methods and apparatus are provided for obtaining a phase offset estimate from a data stream. A binary sampled version of the data stream is obtained based on a clock. A first dot product of the binary sampled version of the data stream and an ideal sequence and a second dot product of the binary sampled version of the data stream and a delayed ideal sequence are accumulated. A phase offset of the clock is adjusted until the accumulated first and second dot product satisfy one or more predefined conditions. For example, the predefined conditions can comprise a transition of at least one of the accumulated first and second dot product or whether at least one of the accumulated first and second dot product transition to a final value.

Abstract: Methods and apparatus are provided for adaptively establishing the optimal sampling phase offset for a DFE operation. According to one aspect of the invention, one or more values in an amplitude domain are converted into a time domain, for example, using a phase detector, based on phase information to provide said sampling phase. The values in the amplitude domain optionally comprise one or more of detected DFE data, ?(n) and a sign of an error term for detected DFE data. The sampling phase can establish the phase of an independent clock or an offset to a second clock, such as a clock recovered from a received signal by a clock and data recovery (CDR) circuit.

Abstract: Disclosed is a system and method for a clock and data recovery (CDR) circuit. A phase selection circuit (PSC) generates a signal comprising frequency and phase. A voltage controlled oscillator (VCO) connected to the PSC generates a clock signal. The clock signal controls the frequency of the signal. The CDR circuit also includes a phase adjustment signal generator connected to the PSC for generating a phase adjustment signal. The phase adjustment signal controls the phase of the signal.

Abstract: Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. In a multi-level implementation, the received signal is sampled using a clock associated with each of the levels and the samples are latched using a vertical slicing technique to generate DFE data associated with each of said levels.

Abstract: A read channel component of a magnetic recording system employs equalization of a signal received from the magnetic recording channel, the equalization being modified depending upon the presence or absence of DC shifts in the signal. Equalization corrects for DC shifts, if present, prior to detection and decoding of servo data, such as servo address mark (SAM) and Gray code data. In a first implementation, a DC shift detector detects the presence or absence of DC shifts and modifies equalization in a predetermined manner. In a second implementation, filtering is applied to the signal to enhance equalization in the presence of DC shift, and both filtered and unfiltered signals employed for detection of the servo data.

Abstract: A repeatable read-out (RRO) detector employs one or more digital interpolators to interpolate asynchronous sample values that represent RRO data. The asynchronous sample values are read from a recording medium and generated by an A/D converter at a symbol rate, and the interpolators generate interpolated samples at at least one time in between the asynchronous sample value times. Each interpolated sample corresponding to some phase relative to that of the sample values generated by the A/D converter. The RRO detector receives 1) the asynchronous samples at symbol rate and 2) the interpolated samples to efficiently detect the encoded RRO data. An RRO address mark indicates when detection of encoded RRO data starts, and is employed to select those samples suitable for RRO data detection. Detection of the RRO address mark employs peak detection among filtered asynchronous and interpolated samples. The process of peak detection adjusts the current best phase for sample selection.

Abstract: The present invention enhances the performance of a clock and data recovery (CDR) circuit by employing look-ahead techniques to produce a low latency timing adjustment. In one example of the invention employed in a CDR circuit having a decimation filter processing the CDR's phase detector output, the invention uses the most significant bits of the decimation filter output to quickly determine a look-ahead adjustment.

Abstract: A first set of data is detected in a signal having synchronous samples and interpolated samples, wherein the first set of data is detected asynchronously as corresponding to one of the samples. A time to transmit a data-found signal is determined based on an offset between the data-detected sample and one of the synchronous samples, and the data-found signal is transmitted at the determined time to enable the synchronous processing of the synchronous samples. In one implementation, the synchronous samples correspond to a readback signal read from a data recording channel, the first set of data corresponds to servo address mark (SAM) data in a servo sector in the readback signal, and the synchronous processing is demodulation of burst data in the servo sector.

Abstract: The present invention utilizes a parallel sampled multi stage decimated digital loop filter for clock and data recovery function. In particular, the present invention provides multiple sampling clocks, with these clocks having sampling clock phases separated in time. These clocks are used in conjunction with multiple data detectors and phase detectors to efficiently process received analog signals in a decimated loop filter system.

Abstract: A recording system, such as a magnetic or optical recording system, employs optimization metrics that are independent of a target partial response for equalization of a signal read from a recording channel. The optimization metrics employ samples adjacent to codeword boundaries of codewords representing encoded data, such as servo data, read from a recording medium. The optimization metrics are used to select filter parameters and/or tap weights for equalization. The filter parameters and/or tap weights might be derived based on the type of data read from the recording medium, the type of detector employed to detect the codewords of the read data, and the type of encoder/decoder employed for the read data.

Abstract: A method and apparatus are disclosed for detecting data, such as a sample sequence read from a recording channel. Interpolation techniques are employed to generate one or more interpolated sample sequences from the data. Each interpolated sample sequence has a different corresponding phase relative to the data. A distance measure is generated between a portion of each interpolated sample sequence and an ideal sample sequence. The ideal sample sequence corresponds to peaks in the data. According to one aspect of the invention, a signal asymmetry measure is computed for the portion of each sample sequence and is used to adjust an ideal sample sequence.