Abstract: Methods and apparatus are provided for more efficiently generating logic for implementing Exclusive OR (XOR) expressions. In one example, multiple centroids are generated and associated with main equations. Both the main equations and centroids are XOR expressions. In particular examples, main equations are associated with centroids that are closest in distance. Centroids can be modified to better match an associated subset of main equations. Centroids are generated and associated until the main equations are expressed as centroids and residue.

Abstract: The present invention relates to a system and a method of improving the debonding of two or more surfaces together. The invention utilises thermoexpanadable microspheres and thermal energy to debond interfaces in an adhesive system or as vehicle carriers. It also discloses a method of curing the adhesive system prior to the debonding step so that the same adhesive system may be used for both phases. It is especially useful in the automotive industry for end of vehicle life dismantling.

Abstract: Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.

Abstract: Methods and apparatus are provided for more efficiently computing error checking codes such as cyclic redundancy checks (CRCs). Based on particular characteristics of CRCs, an input sequence is intelligently divided into a series of subsequences. Each subsequence gets selected bits from the input sequence. The error checking code is calculated on each subsequence. The results are bit-interleaved and an error checking code is calculated over this interleaved result to obtain the error checking code over the entire sequence.

Abstract: If an input word bit includes overhead data, the input word bit is ignored. If the input word bit includes non-overhead data and the corresponding bit position in a first buffer is empty, the non-overhead data is stored in the corresponding bit position in the first buffer, and the corresponding bit position in the first buffer is marked as full. Otherwise, the non-overhead data is stored in the corresponding bit position in a second buffer, and the corresponding bit position in the second buffer is marked as full. When all bit positions in the first buffer are marked as full, the data is shifted out of the first buffer, rotated to be in data arrival sequence, and made available for further processing. Then, the data in the second buffer is transferred to the first buffer, and the bit positions in second buffer are reset to be marked as empty.

Abstract: An apparatus and method for performing multiple exclusive OR (XOR) operations using standard binary multiplication circuitry to create multiple XOR expressions simultaneously. The method and apparatus include a multiplication circuit to generate a product result by performing a multiplication between a multiplier and a multiplicand. A selection circuit is then used to break down the product result into a plurality of partial product sub-expressions. An XOR gate is provided to generate a final expression from one or more of the plurality of partial product sub-expression. The present invention is suited for performing calculations involving a large number of XOR operations with various combinations of product terms, such as cyclical redundancy check calculations.

Abstract: Circuits and methods provide the concurrent calculation of CRC bits for messages from different channels, where one part of a message is received at a time. Context buffers store certain state variables of the CRC calculation for each channel. The context buffers output data in a synchronized manner with the input data so that the proper calculations are done and the proper data is available at the appropriate times.

Abstract: Methods and apparatus are provided for embedding identification information on a programmable chip. Parameterizable components are selected for implementation on a programmable chip. Information relating to the parameterizable components is embedded on the programmable chip by storing the information using mechanisms such as look up tables associated with logic elements. Information can be used to identify types of components, versions of components, parameter sets, and other data associated with components implemented on the programmable device.

Abstract: Method and apparatus for security systems are provided to protect electronic designs from unauthorized usage. An obfuscation system is provided for creating secure simulation models of IP cores that allow efficient evaluation of an electronic design incorporating an IP core but do not allow practical implementation of the IP core. The obfuscation system identifies regions for obfuscation within an IP core. Logic obfuscation is inserted into these regions. Examples of obfuscation include additional circuitry that produces time dilatation, space dilatation, or a combination of the two in the circuitry of an IP core. Typically, the inserted obfuscation does not change the ultimate behavior of the internal signals, but is complicated enough to make an electronic design so slow and/or so large that it cannot be implemented practically. Further, the inserted obfuscation should be of a type is not normally removed by that normal logic optimizations such as synthesis.

Abstract: Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.

Abstract: Circuits, methods, and apparatus for the fast parallel calculation of CRCs. One embodiment provides a feedforward path that combines common terms to simplify input logic. Common expressions that appear in multiple terms in the feedforward path are implemented using logic gates that are shared by the multiple terms, thereby reducing logic complexity, fan-out, and gate delay. Another embodiment provides a CRC logic architecture having a feedback path that is able to use more than one clock cycle in its computation.

Abstract: Cyclic redundancy checking operations may be performed on a message made up of full words and a partial word. An accumulator value for the cyclic redundancy checking operations may be updated as the full words and partial word are processed. The partial word may be padded with pad bits. The effects of the partial word padding can be removed by performing polynomial division on the accumulator. Polynomial division may be performed using an arrangement where each polynomial division involves half as many bits as its predecessor. Iterative division schemes in which a fixed number of bits are processed in multiple passes may also be used. Hybrid arrangements involving cascaded divisions of different orders and iterative fixed-size division can be used. Unpadded partial words may also be processed using cascaded, iterative, and hybrid schemes.

Abstract: The present invention relates to a system and a method of improving the debonding of two or more surfaces together. The invention utilises thermoexpanadable microspheres and thermal energy to debond interfaces in an adhesive system or as vehicle carriers. It also discloses a method of curing the adhesive system prior to the debonding step so that the same adhesive system may be used for both phases. It is especially useful in the automotive industry for end of vehicle life dismantling.

Abstract: The invention relates to a composition, its use and a method of its use as a glazing adhesive. The composition comprises an adhesive agent with thermoexpandable microcapsules which act as pressure actuators dispersed therein. The microcapsules are heat triggered so as to release at least one expandable volatile agent encapsulated within the microcapsule shell.