Abstract: The vessel is generally cube-shaped and has a enclosed hollow interior for cremated remains. The interior is accessible only by the opening and closing of the lower panel of the vessel; otherwise the vessel is inaccessible from the outside. The vessel has decoration for visually distinguishing when the vessel is upright from when it is upside down. The front panel of the vessel has a cavity for receipt of a photograph of the deceased or an inscription.

Abstract: A joint rod adapted for motor vehicles consists of a joint section having a connecting surface and a rod section having an inner surface. The joint section and the rod section being joined by positive engagement between the connecting surface and the inner surface. The rod section is made from a first material and the joint section is made from a second material, the first material and the second material being different from each other.

Abstract: The vessel is generally cube-shaped and has a enclosed hollow interior for cremated remains. The interior is accessible only by the opening and closing of the lower panel of the vessel; otherwise the vessel is inaccessible from the outside. The vessel has decoration for visually distinguishing when the vessel is upright from when it is upside down. The front panel of the vessel has a cavity for receipt of a photograph of the deceased or an inscription.

Abstract: Briefly, in accordance with one embodiment, an integrated circuit includes: electronic circuitry for transferring digital data signals along a digital data signal path between different clock timing domains. The clock timing domains have a common higher frequency source clock. A first clock timing domain clock signal has a relatively fixed phase and a second clock timing domain clock signal has a relatively varying phase. The electronic circuitry includes delay elements in clock signal paths associated with the digital data signal path so that along the digital data signal path, clock signals in different clock timing domains are respectively staggered for a relatively short time compared with a given cycle of the source clock. The electronic circuitry further includes a digital data signal path including a data value retention element to delay the transfer of digital data signals between different clock timing domains at selected times.