Abstract: Digital multiprocessor methods and apparatus comprise a plurality of processors, including a first processor for normally processing an instruction stream including instructions from a first instruction source. At least one of the processors can transmit inserted-instructions to the first processor. Inserted-instructions are executed by the first processor in the same manner as, and without affecting the sequence of, instructions from the first instruction source. The first instruction source can be a memory element, including an instruction cache element for storing digital values representative of instructions and program steps, or an execution unit (CEU) which asserts signals to the instruction cache element to cause instructions to be transmitted to the CEU. The processors include input/output (I/O) processors having direct memory access (DMA) insert elements, which respond to a peripheral device to generate DMA inserted-instructions.

Abstract: A central processing unit for a digital computer. In one embodiment, the central processing unit comprises a plurality of pointer registers that may be used during instruction execution to directly address other registers. In a second embodiment, the central processing unit comprises a size register that is loaded during the decode of an operation code with a size code indicating the data path width for that operation code. During instruction execution, the size code may be used at various times to determine data path width.

Abstract: A central processing unit for a digital computer. In one embodiment, the central processing unit comprises a plurality of pointer registers that may be used during instruction execution to directly address other registers. In a second embodiment, the central processing unit comprises a size register that is loaded during the decode of an operation code with a size code indicating the data path width for that operation code. During instruction execution, the size code may be used at various times to determine data path width.

Abstract: A central processing unit for a digital computer has a central memory unit connected to a system bus. A data path unit decodes variable length microinstructions that are stored in the central memory unit and that include an operation code and one or more operand specifiers, issuing a microaddress of one of a set of microinstructions stored in a control store. The microinstructions have a data path control field, a condition/size field and a next address control field. A microinstruction logic control is responsive to the microinstructions, and a memory control unit that includes a data cache memory array operates asynchronously with respect to the data path unit, translating virtual memory addresses to access data from the data cache memory array or from the central memory unit.