Abstract: An infrared sensor includes a linear array of plural photoconductive sensor elements, and a similarly linear multiplexing circuit arranged in side-by-side relation with the linear array of sensor elements. The multiplexing circuit includes a matching plurality of signal input ports, and a wirebond of plural conductors substantially in parallel conducts signals from the plural sensor elements of the array to the respective signal input ports of the multiplexer circuit. The multiplexer circuit includes a matching plurality of adaptation circuits or cells interposed between the respective sensor elements of the array and the input ports of the multiplexing circuit. Each adaptation cell includes a multi-position switch which by its position varies the transfer function of a feed back circuit of the adaptation cell. Plural modes of signal processing for each individual sensor element of the array are provided according to the positions of the multi-position switches of the plural adaptation cells.

Abstract: An imaging device includes an array of plural imaging elements each of which is responsive to incident light flux to provide an output signal. Each of the imaging elements includes provision for conducting a variable time integration of incident light flux, and alternatively, also for selecting a time interval during which each of the imaging elements simultaneously conducts such a time integration of incident light flux (i.e., takes a snap shot of an image scene). The imaging device includes provision for random access of each image element or group of image elements in the array so that output signals indicative of all or of only selected parts of an imaged scene can be processed for their image information, if desired.

Abstract: An imaging device includes an array of plural imaging elements each of which is responsive to incident light flux to provide an output signal. Each of the imaging elements includes provision for conducting a variable time integration of incident light flux, and alternatively, also for selecting a time interval during which each of the imaging elements simultaneously conducts such a time integration of incident light flux (i.e., takes a snap shot of an image scene). The imaging device includes provision for random access of each image element or group of image elements in the array so that output signals indicative of all or of only selected parts of an imaged scene can be processed for their image information, if desired.

Abstract: The high speed data pathway system is used to convey data signals to integrated circuits connected to mother and daughter boards. The integrated circuits include a package and an integrated circuit chip carried by the package. An internal transmission line is carried by the package and coupled to the integrated circuit chip. The package includes both input and output connections for the internal transmission line. A high speed pathway is formed by serially connecting the internal transmission lines with external transmission lines to form a unified transmission medium. Advantageously, the internal transmission lines, external transmission lines and the connection between them have substantially corresponding characteristic impedances.

Abstract: A very high speed, low power integrated interface circuit using GaAs or InP technology is provided for converting small digital voltage swings to larger swings which are particularly suitable for analog control signals. The preferred embodiments employ solely depletion mode MESFETS and Schottky diodes in Schottky diode field effect logic (SDFL) configurations.

Abstract: An electronic device is provided which includes first and second memory arrays, each capable of storing data at locations therein, and an address decoder positioned between the first and second memory arrays for decoding address signals input thereto and corresponding to the locations. The address decoder is advantageously configured as a set of ISL gates or MESFET logic gates. It is further advantageous to form the memory arrays of Schottky diodes which, when employed with the ISL configuration for an address decoder, utilizes the same Schottky diode in the memory arrays as are utilized in the ISL gates. A further refinement provides a precharged circuit for each bit line.

Abstract: A charge-coupled analogue delay line has a plurality of analogue storage locations, and a gating means, which may include charge-coupled shift register, for enabling input to and output from each of the storage locations in turn. The storage locations are formed on a semiconducting substrate and each has a diffused zener diode to act as a source of minority carriers and a priming electrode for drawing off and holding a charge of minority carriers from the zener diode. A sample-holding electrode, upon receipt of a gating signal by a gating electrode, receives from the priming electrode and holds a charge of minority carriers of magnitude indicative of the magnitude of the signal to be stored. An output electrode is arranged to transfer the charge held by the sample-holding electrode to a diffused output channel.