Abstract: A communication device (e.g., a cable modem (CM)) includes a digital to analog converter (DAC) and a power amplifier (PA) that generate a signal to be transmitting via a communication interface to another communication device (e.g., cable modem termination system (CMTS)). The CM includes diagnostic analyzer that samples the signal based on a fullband sample capture corresponding to a full bandwidth and/or a subset (e.g., narrowband) sample capture to generate a fullband and/or subset signal capture (e.g., of an upstream (US) communication channel between the CM and the CMTS). The diagnostic analyzer can be configured to generate sample captures of the signal based on any desired parameter(s), condition(s), and/or trigger(s). The CM then transmits the signal to the CMTS and the fullband and/or subset signal capture to the CMTS and/or a proactive network maintenance (PNM) communication device to determine at least one characteristic associated with performance of the US communication channel.

Abstract: A communication device (e.g., a cable modem (CM)) includes a digital to analog converter (DAC) and a power amplifier (PA) that generate a signal to be transmitting via a communication interface to another communication device (e.g., cable modem termination system (CMTS)). The CM includes diagnostic analyzer that samples the signal based on a fullband sample capture corresponding to a full bandwidth and/or a subset (e.g., narrowband) sample capture to generate a fullband and/or subset signal capture (e.g., of an upstream (US) communication channel between the CM and the CMTS). The diagnostic analyzer can be configured to generate sample captures of the signal based on any desired parameter(s), condition(s), and/or trigger(s). The CM then transmits the signal to the CMTS and the fullband and/or subset signal capture to the CMTS and/or a proactive network maintenance (PNM) communication device to determine at least one characteristic associated with performance of the US communication channel.

Abstract: Various multi-lane ADCs are disclosed that substantially compensate for impairments present within various signals that result from various impairments, such as phase offset, amplitude offset, and/or DC offset to provide some examples, such that their respective digital output samples accurately represent their respective analog inputs. Generally, the various multi-lane ADCs determine various statistical relationships, such as various correlations to provide an example, between these various signals and various known calibration signals to quantify the phase offset, amplitude offset, and/or DC offset that may be present within the various signals. The various multi-lane ADCs adjust the various signals to substantially compensate for the phase offset, amplitude offset, and/or DC offset based upon these various statistical relationships such that their respective digital output samples accurately represent their respective analog inputs.

Abstract: Various multi-lane ADCs are disclosed that substantially compensate for impairments present within various signals that result from various impairments, such as phase offset, amplitude offset, and/or DC offset to provide some examples, such that their respective digital output samples accurately represent their respective analog inputs. Generally, the various multi-lane ADCs determine various statistical relationships, such as various correlations to provide an example, between these various signals and various known calibration signals to quantify the phase offset, amplitude offset, and/or DC offset that may be present within the various signals. The various multi-lane ADCs adjust the various signals to substantially compensate for the phase offset, amplitude offset, and/or DC offset based upon these various statistical relationships such that their respective digital output samples accurately represent their respective analog inputs.

Abstract: An architecture and method for performing the known windowing and presumming operations associated with enhancing the performance of a fast Fourier transform (FFT) processor is disclosed. The method makes use of a reordering process in order to enable the multiplying and accumulating processes associated with the windowing and presumming operations to be performed on consecutive data points. In order to apply the appropriate coefficients to the multiplier, coefficients are loaded into a series of registers in a loop configuration in which the coefficient in one register is transferred to an adjacent register upon every clock cycle and the last coefficient register transfers its coefficient to the first register. An accumulator accumulates output from the multiplier and applies it to a delay register.