Patents by Inventor Peter Chew

Peter Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230136726
    Abstract: Disclosed is a flexible, scalable method for automatically distinguishing between the ‘mainstream’ and ‘fringe’ in any text dataset, such as unstructured social media data. The disclosed method allows analysts quickly to pinpoint text articulating fringe beliefs or theories, without prior knowledge of the nature of the fringe beliefs, and can be applied to text data in any language, provided the data can be represented electronically. The method works automatically and without any preconceived notions of what is important or what vocabulary is used in the context of certain beliefs. An analyst's attention is then quickly focused either on new conspiracy theories taking hold (potentially allowing decision-makers to act to interdict the ‘next QAnon insurrection’), or on well-founded beliefs that simply are not yet mainstream. Either way, analysts are empowered better to ‘connect the dots’ for a more complete understanding of the information environment.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventor: Peter A. Chew
  • Patent number: 8706758
    Abstract: Disclosed are improvements to a method for account reconciliation comprising improved, extended, and more flexible algorithms for (1) automatically determining what transaction features are best candidates for matching diverse datasets; (2) automatically determining how logically to subdivide accounting datasets prior to reconciliation; (3) matching groups of transactions (allowing one-to-many, many-to-one, and many-to-many matches instead of just one-to-one matches); (4) making use of more types of transaction feature, including transaction dates (where proximity of two transactions in date may be significant even if the dates do not exactly match). The improved method is, therefore, better able to perform its intended function of identifying matching transactions. It is applicable to a wider class of problems while still saving significant costs and labor, and still retaining flexibility in not requiring source data in a particular format, and not being domain-dependent or requiring extensive user setup.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: April 22, 2014
    Assignee: Galisteo Consulting Group, Inc.
    Inventor: Peter A. Chew
  • Patent number: 8685861
    Abstract: A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin insulating layer and the doped insulating layer.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: April 1, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Chih Ping Yong, Peter Chew, Chuin Boon Yeap, Hoon Lian Yap, Ranbir Singh, Nace Rossi, Jovin Lim
  • Patent number: 8639596
    Abstract: Disclosed is a generalized method for automated account reconciliation capable of matching transactions in one accounting dataset to transactions in another accounting dataset with little initial data preparation. The method is highly flexible in that it does not require source data in a particular format, can accept both structured and unstructured (e.g. descriptive text) data as input, is not domain- or language-dependent, and requires little to no training or user-provided heuristics. The method is also adjustable depending on a user's tolerance of error. Based on probability and information theory, computational linguistics, and statistics, the method can complete accounting reconciliation problems in significantly less time than is possible manually, and with just as high accuracy. Especially for large reconciliation problems, the method can save an overwhelming portion of the cost associated with this kind of task in the past.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: January 28, 2014
    Assignee: Galisteo Consulting Group, Inc.
    Inventor: Peter A. Chew
  • Patent number: 8290961
    Abstract: A technique for information retrieval includes parsing a corpus to identify a number of wordform instances within each document of the corpus. A weighted morpheme-by-document matrix is generated based at least in part on the number of wordform instances within each document of the corpus and based at least in part on a weighting function. The weighted morpheme-by-document matrix separately enumerates instances of stems and affixes. Additionally or alternatively, a term-by-term alignment matrix may be generated based at least in part on the number of wordform instances within each document of the corpus. At least one lower rank approximation matrix is generated by factorizing the weighted morpheme-by-document matrix and/or the term-by-term alignment matrix.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: October 16, 2012
    Assignee: Sandia Corporation
    Inventors: Peter A. Chew, Brett W. Bader
  • Publication number: 20100185685
    Abstract: A technique for information retrieval includes parsing a corpus to identify a number of wordform instances within each document of the corpus. A weighted morpheme-by-document matrix is generated based at least in part on the number of wordform instances within each document of the corpus and based at least in part on a weighting function. The weighted morpheme-by-document matrix separately enumerates instances of stems and affixes. Additionally or alternatively, a term-by-term alignment matrix may be generated based at least in part on the number of wordform instances within each document of the corpus. At least one lower rank approximation matrix is generated by factorizing the weighted morpheme-by-document matrix and/or the term-by-term alignment matrix.
    Type: Application
    Filed: January 13, 2009
    Publication date: July 22, 2010
    Inventors: Peter A. Chew, Brett W. Bader
  • Publication number: 20080029853
    Abstract: A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin insulating layer and the doped insulating layer.
    Type: Application
    Filed: August 2, 2006
    Publication date: February 7, 2008
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Chih Ping Yong, Peter Chew, Chuin Boon Yeap, Hoon Lian Yap, Ranbir Singh, Nace Rossi, Jovin Lim
  • Patent number: 6528886
    Abstract: An intermetal dielectric structure for integrated circuits is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: March 4, 2003
    Assignees: Chartered Semiconductor Manufacturing LTD, Lucent Technologies
    Inventors: Huang Liu, John Sudijono, Juan Boon Tan, Edwin Goh, Alan Cuthbertson, Arthur Ang, Feng Chen, Qiong Li, Peter Chew
  • Publication number: 20020130418
    Abstract: An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.
    Type: Application
    Filed: April 29, 2002
    Publication date: September 19, 2002
    Inventors: Huang Liu, John Sudijono, Juan Boon Tan, Edwin Goh, Alan Cuthbertson, Arthur Ang, Feng Chen, Qiong Li, Peter Chew
  • Patent number: 6451687
    Abstract: An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.
    Type: Grant
    Filed: November 24, 2000
    Date of Patent: September 17, 2002
    Assignees: Chartered Semiconductor Manufacturing Ltd., Lucent Technologies Inc.
    Inventors: Huang Liu, John Sudijono, Juan Boon Tan, Edwin Goh, Alan Cuthbertson, Arthur Ang, Feng Chen, Qiong Li, Peter Chew
  • Patent number: 6383922
    Abstract: A method for forming a thermally stable cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the silicon regions to be silicided. A capping layer is deposited overlying the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. A titanium layer is deposited overlying the cobalt monosilicide layer. Thereafter the substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide. The titanium layer provides titanium atoms which diffuse into the cobalt disilicide thereby increasing its thermal stability.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: May 7, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Bei Chao Zhang, Chung Woh Lai, Eng Hua Lim, Mei Sheng Zhou, Peter Chew, Arthur Ang
  • Patent number: 6258676
    Abstract: A Method for forming a shallow trench isolation using HDP silicon oxynitride. A pad oxide layer is formed on a semiconductor substrate having an active area and an isolation area and a barc layer is formed over the pad oxide layer. The barc layer, the pad oxide layer, and the semiconductor substrate are patterned to form a trench having rounded corners in the isolation area. A liner oxide layer is formed over the semiconductor substrate, and a gap fill layer is formed on the liner oxide layer. An important feature of the invention is that the gap fill layer is composed of silicon oxynitride formed using a high density plasma chemical vapor deposition process. A portion of the gap fill layer over the active area can be removed using a reverse trench mask etch, and the gap fill layer is further planarized with a chemical mechanical polishing process using the liner oxide layer as chemical mechanical polishing stop.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: July 10, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kong Hean Lee, Peter Chew
  • Patent number: 5858876
    Abstract: A method for forming a void-free and gap-filling doped silicon oxide insulator layer upon a patterned substrate layer within an integrated circuit. Formed upon a semiconductor substrate is a patterned substrate layer. Formed upon the patterned substrate layer is a doped silicon oxide insulator layer. The doped silicon oxide insulator layer is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method undertaken simultaneously with a Reactive Ion Etch (RIE) etch-back method. The Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etch-back method simultaneously employ a Tetra Ethyl Ortho Silicate (TEOS) silicon source material, a dopant source material, an oxygen source material and an etching gas.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: January 12, 1999
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventor: Peter Chew
  • Patent number: 5618756
    Abstract: A method for selectively depositing WSi.sub.x is described. Semiconductor device structures are provided in and on a semiconductor substrate wherein WSi.sub.x is to be deposited overlying a first portion of the substrate and wherein WSi.sub.x is not to be deposited overlying a second portion of the substrate. A layer of organic material is provided over the surface of the substrate overlying the second portion of the substrate. A layer of WSi.sub.x is deposited over the surface of the substrate wherein the WSi.sub.x is deposited overlying the first portion of the substrate and wherein the presence of the organic material layer prevents the WSi.sub.x from depositing overlying the second portion of the substrate completing the selective WSi.sub.x deposition in the fabrication of an integrated circuit device.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: April 8, 1997
    Assignee: Chartered Semiconductor Manufacturing Pte Ltd.
    Inventors: Peter Chew, Chuck Jang