Abstract: A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.

Abstract: An apparatus includes a read clock path to provide a read clock signal to a memory controller, wherein the read clock signal is to control timing of a memory controller when reading from a memory. The apparatus also includes a write clock path, independent of the read clock path, to provide a write clock signal to the memory controller, wherein the write clock signal is to control timing of the memory controller when writing to the memory.

Abstract: Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented.

Abstract: A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.

Abstract: A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

Abstract: A high speed memory interface for a processor-based computing system provides a bridge component (made up of a controller and a data path), one or more data multiplexer/buffers, and a plurality of RAS/CAS generators. The high speed memory interface allows for the expansion of the memory subsystem without additional loading on the processor/system bus and without a reduction in memory transaction performance. The interface includes a single controller for receiving memory transaction commands from the processor/system bus, and a plurality of RAS/CAS generators, for generating RAS/CAS signals in response to memory transaction commands forwarded by the controller. Each RAS/CAS generator is coupled to one or more memory banks. A data multiplexer/buffer is coupled to one or more of the memory banks, and provides an interface between the memory bank(s) and the data path.

Abstract: A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.

Abstract: A method of arbitrating among bus agents, wherein a bus agent is permitted multiple transactions within a single arbitration cycle. An arbitration event is initiated, and a request from a bus agent is granted to that bus agent for executing a transaction. A timer is started and the transaction is executed. If the timer does not expire before the transaction is completed, another request from that same bus agent is granted to the bus agent for executing an additional transaction before a subsequent arbitration event is initiated.

Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

Abstract: A method and apparatus for ordering data transfers includes an identifier of a critical portion of data being received from a requesting agent along with a request for data. Writeback data corresponding to the requested data is then transferred to the bus as a plurality of portions and ordered to ensure that a first portion which includes the critical portion of the data is transferred to the bus first.

Abstract: A method and apparatus for transferring data between bus agents in a computer system including a bus operating at a bus clock rate. The method includes the step of receiving a transaction request from a requesting agent including an indication of a plurality of data widths the requesting agent processes. In response to the transaction request, a data transmission is configured in accordance with a data width that both the requesting agent and a responding agent process. The data transmission is performed asynchronously with respect to the bus clock if the data width is one of a first plurality of data widths, otherwise, the data transmission is performed synchronously with respect to the bus clock.

Abstract: In a method and apparatus for changing data transfer widths in a computer system, a first agent on a bus provides a first indication to a second agent on the bus identifying one or more data transfer widths supported by the first agent. The second agent then provides a second indication to the first agent identifying one or more data transfer widths supported by the second agent. A data transfer width is then determined based on the first indication and the second indication. According to an embodiment of the present invention, a third agent involved in a transaction is also able to provide a third indication to the first and/or second agents identifying one or more data transfer widths supported by the third agent. The data transfer width(s) is then determined based on the first, second, and third indications.

Abstract: Prior art methods of maintaining coherency among multiple TLBs in a multiprocessor system were time-consuming. One microprocessor halted all other microprocessors in the system, and sent an interrupt to each of the halted microprocessors. Rather than invoking an interrupt handler, the TLB shootdown operation of the present invention provides for a TLB flush transaction communicated between multiple processors on a host bus. One microprocessor issues a TLB flush request on the host bus. The TLB flush request includes a page number. The microprocessors receiving the request invalidate the TLB entry corresponding to the page number.

Abstract: A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlock-free operation. I/O to memory transactions and processor to memory transactions are placed in a memory request queue in the order in which such transactions appear on the processor bus; I/O to memory transactions are placed in an inbound request queue in the order such transactions appear on the I/O bus; and processor to I/O transactions and completions corresponding to split-transaction I/O to memory read transactions are placed in an outbound request queue in the order in which the split-transaction I/O to memory read transactions and the processor to I/O transactions appear on the processor bus.

Abstract: A computer memory subsystem and associated method are disclosed in which memory transaction latency and bandwidth in the memory subsystem are improved through the opportunistic transfer of write data from a data path to a memory buffer coupled to a targeted memory bank during an access latency period within a non-memory write operation, such as, e.g., a read or refresh operation. The opportunistic write data transfer operation utilizes otherwise unused memory data bus cycles within a read or refresh operation for performance of the write data transfer, without adding clock cycles to the read or refresh operation. Because the write data is transferred to the memory buffer coupled to the memory bank during the latency period of the memory operation preceding the write operation, the total turnaround time for, e.g., performing a read operation followed by a write operation is reduced.

Abstract: Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented.

Abstract: A control mechanism is provided for controlling the operation of a memory device. The control mechanism is contained within the memory device, and includes a buffer that receives data stored in the memory device and transmits the data to an output of the memory device. A logic device is coupled to the buffer controls the flow of data through the buffer by generating an output enable signal. The control mechanism may also include a counter coupled to a memory array. The counter identifies a memory entry within the memory array. A logic device is coupled to the counter and controls the operation of the counter.

Abstract: A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

Abstract: A dynamic pipeline depth control method and apparatus is used with a bus which supports pipelined bus transactions. An agent coupled to the bus includes both a transmitter and a receiver. The transmitter is used to transmit an indication to the other agents coupled to the bus which prevents the other agents from issuing a transaction on the bus. The receiver is used to receive the indication, from another agent, that prevents the agent from issuing a transaction on the bus.