Patents by Inventor Peter Dean
Peter Dean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7158186Abstract: A video display system is disclosed. The video display system comprises a display generator for providing a display timing signal and a frame rate converter for receiving input video data, input video timing, and for providing output video data. The system includes a control logic for receiving a frame rate indication signal, the video input timing and the display timing signal. The control logic changes the display frame rate of the display generator in accordance with the native frame rate of the program, and in such a way as to maintain a stable image throughout.Type: GrantFiled: May 27, 2003Date of Patent: January 2, 2007Assignee: Genesis Microchip Inc.Inventors: Steve Selby, Peter Dean Swartz
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Publication number: 20060263219Abstract: A boat propeller comprising a central hub member and an inner hub assembly that defines a longitudinally extending bore having an inner surface. The exterior surface of the central hub member is sized and shaped for disposition therein the bore of the inner hub assembly in a complementary fashion. In one aspect, the propeller may also comprise a plurality of resilient spacer members positioned such that that the exterior surface of the central hub member is spaced from the inner surface of the bore.Type: ApplicationFiled: May 19, 2005Publication date: November 23, 2006Inventor: Peter Dean
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Patent number: 6970816Abstract: A method and system for efficiently generating parameterized bus transactions for verification of a design-under-test (DUT) comprises providing a configuration file for the DUT to a generator program. The configuration file defines possible parameter combinations for bus transactions executable by the DUT, and the generator program systematically enumerates all the possible combinations to produce a test case for verifying the DUT. Rules specified within the configuration file can include or exclude selected parameter combinations to tailor the test case to a specific DUT-to-bus interface.Type: GrantFiled: August 14, 2000Date of Patent: November 29, 2005Assignee: International Business Machines CorporationInventors: Paul David Bryan, Richard Gerard Hofmann, Peter Dean LaFauci, William Robert Lee, Rhonda Gurganious Mitchell, Timothy Patrick Oke
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Publication number: 20050153620Abstract: A toy glider including a shaft, a roller attached to a first end of the shaft, and a housing attached to a second opposing end of the shaft. The roller, a front end portion of the housing, and other portions of the toy glider are interchangeable to create a variety of different designs.Type: ApplicationFiled: January 12, 2004Publication date: July 14, 2005Inventors: Anatol Wizenberg, Peter Dean, Wai Choi, Ming Chan, Lai Man
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Patent number: 6829731Abstract: A method and system for automating the creation of test cases for logic designs. A comprehensive set of bus transactions characterizing a bus architecture is provided to a test case designer in a user interface. The designer may enter inputs corresponding to a particular design-under-test (DUT) via the interface. The interface processes the inputs to automatically generate a configuration file corresponding to the particular DUT. The configuration file may be processed by a generator program to automatically generate a test case comprising one or more bus transactions customized to the particular DUT.Type: GrantFiled: August 14, 2000Date of Patent: December 7, 2004Assignee: International Business Machines CorporationInventors: Peter Dean LaFauci, Rhonda Gurganious Mitchell, Jeffrey Richard Summers
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Publication number: 20040239803Abstract: A video display system is disclosed. The video display system comprises a display generator for providing a display timing signal and a frame rate converter for receiving input video data, input video timing, and for providing output video data. The system includes a control logic for receiving a frame rate indication signal, the video input timing and the display timing signal. The control logic changes the display frame rate of the display generator in accordance with the native frame rate of the program, and in such a way as to maintain a stable image throughout.Type: ApplicationFiled: May 27, 2003Publication date: December 2, 2004Inventors: Steve Selby, Peter Dean Swartz
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Patent number: 6772254Abstract: A multi-master computer system having overlapped read and write signal with scalable address pipelining programmable increases the depth of address pipelining independently on two overlapped read and write data busses up to “N” deep requests. The system includes a local bus having an address bus, a read bus, and a write bus. Master devices are coupled to separate address, read data and write data buses. Slave devices are attached to the data busses through shared, but decoupled address, read and write data buses. An arbiter is coupled to the data bus and allows masters to compete for bus ownership. The arbiter includes read and write pipeline logic for processing and priortizing master and slave read and write data transfers across the data bus.Type: GrantFiled: May 15, 2001Date of Patent: August 3, 2004Assignee: International Business Machines CorporationInventors: Richard Gerard Hofmann, Jason Michael Hopp, Peter Dean LaFauci, Dennis Charles Wilkerson
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Patent number: 6718521Abstract: A method and system for easily and automatically determining the extent of test coverage for a design-under-test (DUT). Incremental test coverage information is gathered from the application of test cases to the DUT, and cumulative test coverage information is maintained. The incremental test coverage and cumulative test coverage information are fed into a correlation process, which correlates valid bus transactions automatically generated from a configuration file describing the DUT with the incremental and cumulative test coverage information. The correlation process determines which valid bus transactions have or have not been applied in testing the DUT.Type: GrantFiled: August 14, 2000Date of Patent: April 6, 2004Assignee: International Business Machines CorporationInventors: David Gary Bentlage, Paul David Bryan, Peter Dean LaFauci, Randall Rogers Pratt
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Patent number: 6699016Abstract: An improved watercraft propeller is provided with a hub having a plurality of outwardly extending blades, and at least one reverse thrust member connected to a selected blade of the propeller. The blade to which the reverse thrust member is connected can provide a blade pitch that is constant, variable, progressive, or regressive. The reverse thrust member is formed integrally with or connected to a leading edge of the selected blade. The reverse thrust member effectively increases the pitch of the propeller when operated to propel a watercraft in a reverse direction, thereby improving the performance and efficiency of the propeller.Type: GrantFiled: June 12, 2002Date of Patent: March 2, 2004Inventor: Peter Dean
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Patent number: 6684277Abstract: The present invention provides a method and computer readable medium with program instructions for automatically verifying bus transactions. The method includes: parsing a parameter code for the bus transactions, wherein the parameter code comprises a plurality of expected parameter values for the bus transactions; automatically integrating the parsed parameter code into a checking program; and automatically executing the checking program, wherein the checking program compares the plurality of expected parameter values with a plurality of actual parameter values for the bus transactions. The bus transaction verification method in accordance with the present invention automates the coding of expected parameter values for each test case into a checking program and automates the execution of the checking program, where the checking program compares the expected parameter values with the actual parameter values.Type: GrantFiled: January 26, 2001Date of Patent: January 27, 2004Assignee: International Business Machines CorporationInventors: Peter Dean LaFauci, Bryan Heath Stypmann, Paul David Bryan
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Patent number: 6587905Abstract: A high performance integrated circuit (IC) with independent read and write data busses enables full simultaneous read and write data transfers between devices coupled to the buses. Multiple master and multiple slave devices communicate using the resources of a bus controller and a bus arbiter. Having separate read and write data busses with separate and independent arbitration allows reads and writes from different devices to occur simultaneously. Many high performance IC, like systems on a chip (SOC), have many different functional units communicating with a central processing unit (CPU). Many such CPUs have architectures that may cause in certain applications an unbalance between read and write traffic on the independent busses. Master and slave devices contain auxiliary internal read and write data buses multiplexed such that read or write data may be interchanged.Type: GrantFiled: June 29, 2000Date of Patent: July 1, 2003Assignee: International Business Machines CorporationInventors: Anthony Correale, Jr., Richard Gerard Hofmann, Peter Dean LaFauci, Dennis Charles Wilkerson
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Patent number: 6513089Abstract: The present invention discloses a method and system for managing independent read and write buses by dividing the pending read and write request signals and the read and write request priority level signals. The arbitration for use of the read and write buses are done independently for the read and write operations. A higher priority read, for example, can be concurrent with a corresponding lower priority write. Interruption of in process reads or writes is also done using the split arbitrations of the read and write buses leading the disruption of lower priority operations only if the conflicts are concurrent for the same read or write operation.Type: GrantFiled: May 18, 2000Date of Patent: January 28, 2003Assignee: International Business Machines CorporationInventors: Richard Gerard Hofmann, Peter Dean LaFauci, Dennis Charles Wilkerson
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Patent number: 6507808Abstract: An apparatus and method for hardware logic verification data transfer checking are implemented. Data for transfer is generated in response to a decoded bus transaction instruction using a pseudorandom number generator. The seed for the generator includes a predetermined portion provided to each bus device. The predetermined portion is combined with the address of the target device, obtained from the decoded instruction, to form the seed input to the random number generator. For write transactions, the bus master generates the data to be transferred using the seed, and sends the data to the target. The target independently generates the data by a call to the random number generator and compares the value received via the data transfer with the independently generated value. Similarly, for read transactions, the slave device generates the data to be transferred in response to the read request.Type: GrantFiled: June 23, 1999Date of Patent: January 14, 2003Assignee: International Business Machines CorporationInventor: Peter Dean LaFauci
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Patent number: 6430641Abstract: Methods, arbiters, and computer program products determine if a request for an idle bus in a dual bus data processing system is being blocked by one or more pending requests for the other bus. In this circumstance, any such pending request for the other bus is masked by the arbiter so that the request for the idle bus can be granted. Consequently, a more efficient utilization of the dual bus architecture is achieved. In an illustrative embodiment, a bus request is received for a first one of the dual busses. If the address and control busses are unavailable to allow the request to be granted, then an inquiry is made regarding the status of a pending request for the second one of the dual busses that has gained control of the address and control busses. In particular, it is determined whether a primary request has been granted and a secondary request has been pipelined for the second one of the dual busses.Type: GrantFiled: May 4, 1999Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Richard Gerard Hofmann, Peter Dean LaFauci, Dennis Charles Wilkerson
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Patent number: 6401349Abstract: A stylus is carried at one end of a support arm mounted so as to be pivotable about a pivot axis to allow the stylus to follow a surface during relative movement between the stylus and the surface. A drive arrangement is responsive to pivotal movement of the support arm to drive the support arm to maintain the support arm at a substantially constant attitude. A measuring arrangement is provided for measuring the displacement of the stylus. The measuring arrangement uses a measuring element mounted to one end of the support arm adjacent the stylus. The measuring arrangement may be an interferometer and the measuring element a corner cube mounted so as to be aligned with the tip of the stylus.Type: GrantFiled: August 4, 1998Date of Patent: June 11, 2002Assignee: Taylor Hobson LimitedInventor: Peter Dean Onyon
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Publication number: 20020062414Abstract: A multi-master computer system having overlapped read and write signal with scalable address pipelining programmable increases the depth of address pipelining independently on two overlapped read and write data busses up to “N” deep requests. The system includes a local bus having an address bus, a read bus, and a write bus. Master devices are coupled to separate address, read data and write data buses. Slave devices are attached to the data busses through shared, but decoupled address, read and write data buses. An arbiter is coupled to the data bus and allows masters to compete for bus ownership. The arbiter includes read and write pipeline logic for processing and priortizing master and slave read and write data transfers across the data bus.Type: ApplicationFiled: May 15, 2001Publication date: May 23, 2002Applicant: International Business Machines CorporationInventors: Richard Gerard Hofmann, Jason Michael Hopp, Peter Dean LaFauci, Dennis Charles Wilkerson