Patents by Inventor Peter Elenius

Peter Elenius has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8487437
    Abstract: An electronic device package includes a substrate assembly, an electronic device disposed to face the substrate assembly, and a sealing ring or rings including a sealing layer and a bonding layer that is disposed between the substrate assembly and the electronic device, wherein the sealing ring(s) has a closed loop shape surrounding a sealing region of the electronic device, and the bonding layer is formed through a reaction of the sealing layer and sealing layer pad with a low-melting-point material layer whose melting point is lower than that of the sealing layer and sealing ring pad. The bonding layer is formed of an intermetallic compound of the sealing layer, sealing ring pad and low-melting-point material that melts at a temperature greater than the melting temperature of the low-melting-point material. The device package also includes electrical connections in the form of joints between the substrate assembly and electronic device.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: July 16, 2013
    Assignee: Optopac Co., Ltd.
    Inventors: Peter Elenius, Deok Hoon Kim, Young Sang Cho
  • Patent number: 8141245
    Abstract: A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: March 27, 2012
    Assignee: PPG Industries Ohio, Inc
    Inventors: Kevin C. Olson, Alan E. Wang, Peter Elenius, Thomas W. Goodman
  • Publication number: 20110193231
    Abstract: An electronic device package includes a substrate assembly, an electronic device disposed to face the substrate assembly, and a sealing ring or rings including a sealing layer and a bonding layer that is disposed between the substrate assembly and the electronic device, wherein the sealing ring(s) has a closed loop shape surrounding a sealing region of the electronic device, and the bonding layer is formed through a reaction of the sealing layer and sealing layer pad with a low-melting-point material layer whose melting point is lower than that of the sealing layer and sealing ring pad. The bonding layer is formed of an intermetallic compound of the sealing layer, sealing ring pad and low-melting-point material that melts at a temperature greater than the melting temperature of the low-melting-point material. The device package also includes electrical connections in the form of joints between the substrate assembly and electronic device.
    Type: Application
    Filed: September 17, 2010
    Publication date: August 11, 2011
    Applicant: OPTOPAC CO., LTD.
    Inventors: Peter ELENIUS, Deok Hoon KIM, Young Sang CHO
  • Publication number: 20090101274
    Abstract: A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.
    Type: Application
    Filed: December 29, 2008
    Publication date: April 23, 2009
    Inventors: Kevin C. Olson, Alan E. Wang, Peter Elenius, Thomas W. Goodman
  • Patent number: 7485812
    Abstract: A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.
    Type: Grant
    Filed: November 11, 2004
    Date of Patent: February 3, 2009
    Assignee: PPG Industries Ohio, Inc.
    Inventors: Kevin C. Olson, Alan E. Wang, Peter Elenius, Thomas W. Goodman
  • Publication number: 20080302564
    Abstract: A substrate for an electronic device package includes an electrically conductive core shaped to define a cavity for receiving an electronic device, a first insulating layer positioned on a first side of the core, and a first contact positioned adjacent to a surface within the cavity. Method of fabricating the substrates is also provided.
    Type: Application
    Filed: June 11, 2007
    Publication date: December 11, 2008
    Applicant: PPG INDUSTRIES OHIO, INC.
    Inventors: Kevin C. Olson, Thomas W. Goodman, Peter Elenius
  • Patent number: 7126164
    Abstract: A wafer-level CSP (200) includes at least one die (202) from a wafer. The wafer-level CSP has a plurality of solder ball pads (206), a solder ball (308) at each solder ball pad and a polymer collar (310) around each solder ball. A moat (204) is formed in the surface of a polymer layer (412) disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual (502) from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region (314) defined by the moat. A full-depth moat (312) extends completely through the polymer layer. Alternatively, a partial-depth moat (712 and 912) extends partially through the polymer layer.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: October 24, 2006
    Assignee: FlipChip International LLC
    Inventors: Michael E. Johnson, Peter Elenius, Deok Hoon Kim
  • Patent number: 7118833
    Abstract: A photomask (1900) for producing partial-depth features (712 and 912) in a photo-imageable polymer layer (412) on a wafer of a chip scale package (200) using exposure tools capable of resolving sizes of a critical dimension or larger, has a plurality of chrome lines (2101–2103). Each chrome line has a width (2105) that is less than the critical dimension, and each chrome line of the plurality of chrome lines is spaced apart less than the critical dimension. The plurality of chrome lines produces a single partial-depth feature, such as a via, through part of a thickness of the polymer layer. Alternatively, the photomask has a plurality of chrome circles (2206), each chrome circle having a diameter less than the critical dimension and being spaced apart less than the critical dimension, which produces the partial-depth feature.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: October 10, 2006
    Assignee: FlipChip International, LLC
    Inventors: Peter Elenius, Michael E. Johnson
  • Patent number: 7057292
    Abstract: A solder bar compatible with conventional flip chip technology fabrication methods for high power/high current applications includes first and second generally circular solder pads of diameter D formed upon a substrate and connected by a solder bar pad of width BW. The centers of the generally circular solder pads are spaced apart by distance BL (bar length). A mass of solder having volume VB is formed over the first and second generally circular solder pads and over the solder bar pad to form a dog-bone shaped solder bar. The solder bar reaches height H1 above the centers of the first and second generally circular solder pads, and reaching height H2 above the midpoint of the solder bar pad. The values for diameter D, bar length BL, bar width BW, and solder volume VB are selected in such manner that H1 and H2 are approximately equal.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: June 6, 2006
    Assignee: FlipChip International, LLC
    Inventors: Peter Elenius, Hong Yang
  • Publication number: 20050124196
    Abstract: A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.
    Type: Application
    Filed: November 11, 2004
    Publication date: June 9, 2005
    Inventors: Kevin Olson, Alan Wang, Peter Elenius, Thomas Goodman
  • Publication number: 20050070083
    Abstract: A wafer-level CSP (200) includes at least one die (202) from a wafer. The wafer-level CSP has a plurality of solder ball pads (206), a solder ball (308) at each solder ball pad and a polymer collar (310) around each solder ball. A moat (204) is formed in the surface of a polymer layer (412) disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual (502) from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region (314) defined by the moat. A full-depth moat (312) extends completely through the polymer layer. Alternatively, a partial-depth moat (712 and 912) extends partially through the polymer layer.
    Type: Application
    Filed: September 26, 2003
    Publication date: March 31, 2005
    Inventors: Michael Johnson, Peter Elenius, Deok Kim
  • Publication number: 20050069782
    Abstract: A photomask (1900) for producing partial-depth features (712 and 912) in a photo-imageable polymer layer (412) on a wafer of a chip scale package (200) using exposure tools capable of resolving sizes of a critical dimension or larger, has a plurality of chrome lines (2101-2103). Each chrome line has a width (2105) that is less than the critical dimension, and each chrome line of the plurality of chrome lines is spaced apart less than the critical dimension. The plurality of chrome lines produces a single partial-depth feature, such as a via, through part of a thickness of the polymer layer. Alternatively, the photomask has a plurality of chrome circles (2206), each chrome circle having a diameter less than the critical dimension and being spaced apart less than the critical dimension, which produces the partial-depth feature.
    Type: Application
    Filed: September 26, 2003
    Publication date: March 31, 2005
    Inventors: Peter Elenius, Michael Johnson
  • Patent number: 6750135
    Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: June 15, 2004
    Assignee: Flip Chip Technologies, L.L.C.
    Inventors: Peter Elenius, Harry Hollack
  • Patent number: 6578755
    Abstract: A method of forming a polymer support ring, or collar, around the base of solder balls used to form solder joints includes forming patterned regions of uncured polymer material over each of the conductive solder bump pads on an IC package or other substrate to which the solder balls are to be attached. Preferably, the uncured polymer material is a no-flow underfill material that fluxes the solder bump pads. Pre-formed solder balls are then placed into the uncured polymer material onto their respective solder bump pads. A subsequent heating cycle raises the assembly to the reflow temperature of the solder balls, thereby attaching the solder balls to the underlying solder bump pads, and at least partially curing the polymer material to form a support collar at the base region of each attached solder ball.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: June 17, 2003
    Assignee: Flip Chip Technologies, L.L.C.
    Inventors: Peter Elenius, Deok-Hoon Kim
  • Patent number: 6441487
    Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: August 27, 2002
    Assignee: Flip Chip Technologies, L.L.C.
    Inventors: Peter Elenius, Harry Hollack
  • Publication number: 20010031548
    Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.
    Type: Application
    Filed: June 20, 2001
    Publication date: October 18, 2001
    Inventors: Peter Elenius, Harry Hollack
  • Patent number: 6287893
    Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: September 11, 2001
    Assignee: Flip Chip Technologies, L.L.C.
    Inventors: Peter Elenius, Harry Hollack
  • Publication number: 20010011764
    Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.
    Type: Application
    Filed: October 20, 1997
    Publication date: August 9, 2001
    Inventors: PETER ELENIUS, HARRY HOLLACK
  • Patent number: 5397604
    Abstract: This invention is an improved method and apparatus for applying fluids onto a selected area of a component. The method uses a thin film or membrane formed by placing a forming tool in the fluid to be applied. A thin film or membrane is formed across the forming tool, which is analogous to a soap bubble formed across a bubble wand dipped into a soap bubble solution. The thin film is brought into contact with the area of the component to be coated thereby resulting in the transfer of the thin film onto the component and a variation of the thin fluid film or membrane forming tool that allows for a continuous feed application.
    Type: Grant
    Filed: December 3, 1993
    Date of Patent: March 14, 1995
    Assignee: International Business Machines Corporation
    Inventors: Robert P. Phillips, III, Norman J. Dauerer, Peter Elenius, Brian M. Kerrigan, Helmut Krueger, Robert O. Lussow