Abstract: A loop-back self-test circuit (10) that has particular application for a cellular telephone base station, where the components of the self-test circuit (10) are integrated on a common integrated circuit chip (20). The transmit signal and an LO signal are applied to a mixer (28) to convert the frequency of the transmit signal to the frequency of a receive signal. A VCO (56) generates the LO signal and a PLL (26) synchronizes the phase of the VCO signal to the phase of a reference signal. A divided reference signal and a divided VCO signal are applied to a phase comparator (52) that generates an error signal indicative of the phase difference between the reference signal and the VCO signal. The error signal is applied to a charge pump (60) that generates a current signal to tune a tank circuit (66). A voltage signal from a loop filter (62) is applied to the VCO (56) to tune it to the LO frequency.

Abstract: An EER amplifier for amplifying an RF signal includes: (II) a first RF amplifier for amplifying the phase portion of the signal; (III) an EER modulator for amplifying the envelope or baseband portion of the signal, including: A) a high frequency operational amplifier; B) a power amplifier; C) a feedback control loop including: (1) a current-to-voltage conversion amplifier having an input coupled to a current monitoring output of the power amplifier and an output, (2) an input buffer amplifier having an input coupled to receive the envelope signal and an output; (3) a summing amplifier having: (a) an input coupled to the outputs of: (a) the current-to-voltage conversion amplifier and (b) the input buffer amplifier, and (b) an output coupled to the current control input of the power amplifier.

Abstract: A cascadable divide-by-two binary counter circuit (120) that has particular application for use as a synchronous divider circuit (50, 54) in a phase lock loop (26). The counter circuit (120) employs a D flip-flop (122) that receives a D input and provides a Q output. A first AND gate (124) is responsive to a P input and a Q input, where the Q input is the output from a preceding counter circuit and the P input is the state of all of the preceding counter circuits. The output of the AND gate (124) is applied to an exclusive-OR gate (126) along with the Q output of the flip-flop (122). The output of the exclusive-OR gate (126) is applied to one input of a second AND gate (128). The other input of the second AND gate (128) is a reset signal and the output of the second AND gate (128) is the D input of the flip-flop (122). A decoder (142) is programmed to provide the reset signal when the desired count is reached.

Abstract: A rail-to-rail charge pump circuit (60) that provides a current source and a current sink to a loop filter (62). The circuit (60) is responsive to two differential logic signals from a phase comparator (52) that compares the phase of a divided down voltage controlled oscillator signal to a reference signal. The charge pump circuit (60) employs complimentary pairs of PNP and NPN bipolar transistors. One of the input signals from the phase comparator (52) is applied to the base terminal of a bipolar transistor (104) that generates a mirror current in another bipolar transistor (108) to provide the source current. The other input signal from the phase comparator (52) is applied to the base terminal of a bipolar transistor (94) that generates a mirror current in another bipolar transistor (98) to provide the sink current. A bleed resistor (114) is coupled to the base terminal of the bipolar transistor (104) so that the circuit (60) always provides a constant phase comparator gain.

Abstract: A loop-back self-test circuit (10) that has particular application for a cellular telephone base station, where the components of the self-test circuit (10) are integrated on a common integrated circuit chip (20). The transmit signal and an LO signal are applied to a mixer (28) to convert the frequency of the transmit signal to the frequency of a receive signal. A VCO (56) generates the LO signal and a PLL (26) synchronizes the phase of the VCO signal to the phase of a reference signal. A divided reference signal and a divided VCO signal are applied to a phase comparator (52) that generates an error signal indicative of the phase difference between the reference signal and the VCO signal. The error signal is applied to a charge pump (60) that generates a current signal to tune a tank circuit (66). A voltage signal from a loop filter (62) is applied to the VCO (56) to tune it to the LO frequency.

Abstract: A rail-to-rail charge pump circuit (60) that provides a current source and a current sink to a loop filter (62). The circuit (60) is responsive to two differential logic signals from a phase comparator (52) that compares the phase of a divided down voltage controlled oscillator signal to a reference signal. The charge pump circuit (60) employs complimentary pairs of PNP and NPN bipolar transistors. One of the input signals from the phase comparator (52) is applied to the base terminal of a bipolar transistor (104) that generates a mirror current in another bipolar transistor (108) to provide the source current. The other input signal from the phase comparator (52) is applied to the base terminal of a bipolar transistor (94) that generates a mirror current in another bipolar transistor (98) to provide the sink current. A bleed resistor (114) is coupled to the base terminal of the bipolar transistor (104) so that the circuit (60) always provides a constant phase comparator gain.

Abstract: A cascadable divide-by-two binary counter circuit (120) that has particular application for use as a synchronous divider circuit (50, 54) in a phase lock loop (26). The counter circuit (120) employs a D flip-flop (122) that receives a D input and provides a Q output. A first AND gate (124) is responsive to a P input and a Q input, where the Q input is the output from a preceding counter circuit and the P input is the state of all of the preceding counter circuits. The output of the AND gate (124) is applied to an exclusive-OR gate (126) along with the Q output of the flip-flop (122). The output of the exclusive-OR gate (126) is applied to one input of a second AND gate (128). The other input of the second AND gate (128) is a reset signal and the output of the second AND gate (128) is the D input of the flip-flop (122). A decoder (142) is programmed to provide the reset signal when the desired count is reached.

Abstract: A system for high-density data recording at low tape speeds receives a unipolar signal representing encoded digital data and transforms it to a bipolar signal having a constant pulse width. The low-frequency response required of the system is minimized because the power spectrum of the signal is altered through a time domain transformation. The narrow bandwidth enables the use of very low tape speeds at high bit packing densities. Tape speeds of 15/32 ips or less at densities about 20 thousand (k) bits per inch (BPI) are possible. The spectrum of the transformed code has no direct current (DC) component which eliminates the need for a base line compensator in the reproducing portion of the system.